Altera Transceiver PHY IP Core User Manual
Page 447
Table 14-26: Interlaken Frame Generator Parameters
Parameter
Range
Description
teng_tx_framgen_enable
On/Off
When you turn this option On, the
frame generator block of the 10G PCS is
enabled.
teng_tx_framgen_user_length
0-8192
Specifies the metaframe length.
teng_tx_framgen_burst_enable
On/Off
When you turn this option On, the
frame generator burst functionality is
enabled.
Enable tx_10g_frame port
On/Off
When you turn this option On, the 10G
PCS includes the
tx_10g_frame
output
port. When asserted,
tx_10g_frame
indicates the beginning of a new
metaframe inside the frame generator.
Enable tx_10g_frame_diag_status port
On/Off
When you turn this option On, the 10G
PCS includes the
tx_10g_frame_diag_
status
2-bit input port. This port
contains the lane Status Message from
the framing layer Diagnostic Word,
bits[33:32]. This message is inserted into
the next Diagnostic Word generated by
the frame generation block. The
message must be held static for 5 cycles
before and 5 cycles after the
tx_frame
pulse.
Enable tx_10g_frame_burst_en port
On/Off
When you turn this option On, the 10G
PCS includes the
tx_10g_frame_burst_
en
input port. This port controls frame
generator data reads from the TX FIFO.
The value of this signal is latched once at
the beginning of each Metaframe. It
controls whether data is read from the
TX FIFO or SKIP Words are inserted
for the current Metaframe. It must be
held static for 5 cycles before and 5
cycles after the
tx_frame
pulse. When
tx_10g_frame_burst_en
is 0, the frame
generator does not read data from the
TX FIFO for current Metaframe. It
insert SKIPs. When
tx_10g_frame_
burst_en
is 1, the frame generator reads
data from the TX FIFO for current
Metaframe.
Interlaken Frame Synchronizer
The Interlaken frame synchronizer block achieves lock by looking for four synchronization words in
consecutive metaframes. After synchronization, the frame synchronizer monitors the scrambler word in
the metaframe and deasserts the lock signal after three consecutive mismatches and starts the synchroni‐
14-36
10G PCS Parameters for Arria V GZ Native PHY
UG-01080
2015.01.19
Altera Corporation
Arria V GZ Transceiver Native PHY IP Core