Low latency phy analog parameters, Low latency phy analog parameters -12 – Altera Transceiver PHY IP Core User Manual
Page 259
TX PLL (0–3)
(Refer to
Low Latency PHY General Options
for a detailed explanation of these parameters.)
Reference clock frequency
Variable
Specifies the frequency of the PLL input
reference clock. The PLL must generate an
output frequency that equals the Base data
rate/2. You can use any Input clock
frequency that allows the PLLs to generate
this output frequency.
Selected reference clock source
0–4
Specifies the index of the input clock for this
TX PLL. Logical index 0 corresponds to
input clock 0 and so on.
Channel Interface
Enable Channel Interface
On/Off
Turn this option on to enable PLL and
datapath dynamic reconfiguration. When
you select this option, the width of
tx_
parallel_data
and
rx_parallel_data
buses increases in the following way.
• Standard datapath:
• The
tx_parallel_data
bus is 44 bits per
lane; however, only the loworder number
of bits specified by the FPGA fabric
transceiver interface width contain valid
data for each lane.
• The
rx_parallel_data
bus is 64 bits per
lane; however, only the loworder number
of bits specified by the FPGA fabric
transceiver interface width contain valid
data.
• 10G datapath:
• The both the
tx_parallel_data
and
rx_
parallel_data
buses are 64 bits per
lane; however, only the loworder number
of bits specified by the FPGA fabric
transceiver interface width contain valid
data.
Related Information
•
on page 16-33
•
on page 10-4
Low Latency PHY Analog Parameters
For analog parameters refer to Analog Settings for Stratix V Devices.
10-12
Low Latency PHY Analog Parameters
UG-01080
2015.01.19
Altera Corporation
Low Latency PHY IP Core