Altera Transceiver PHY IP Core - Manual (Page 662)

Chapter Document
Version
Changes Made
1G/10Gbps Ethernet
PHY IP Core
2.7 Made the following changes:
• Updated the chapter to indicate new IP instantiation flow using
the IP Catalog.
• Changed the device family support to final for this IP core in
Table 5-2: Device Family Support.
• Removed erroneous references to 10GBBASE-KR PHY IP Core
from this chapter.
• Updated the description of rx_clkslip signal in 1G/10GbE Control
and Status Interfaces.
XAUI PHY IP Core 2.7 Made the following changes:
• Updated the description of
rx_digitalreset
and
tx_digital-
reset
signals in Table 6-10: Optional Clock and Reset Signals.
• Updated Figure 6-4: XAUI Top-Level Signals - Soft PCS and
PMA.
• Added the description of
xgmii_tx_clk
and
xgmii_rx_clk
in
Table 6-10: Optional Clock and Reset Signals.
Interlaken PHY IP
Core
2.7 Made the following changes:
• Updated the chapter to indicate new IP instantiation flow using
the IP Catalog.
• Changed the device family support to final for this IP core in the
Table 7-1 Device Family Support.
• Updated the descriptions of
rx_dataout_bp
and
tx_user_
clkout
signals in Table 7-5: Avalon-ST RX Signals.
PHY IP Core for PCI
Express
2.7 Made the following changes:
• Updated the chapter to indicate new IP instantiation flow using
the IP Catalog.
• Changed the device family support to final for this IP core in
Table 8-1: Device Family Support.
• Updated Table 8-4: Preset Mappings to TX De-Emphasis.
21-2 Additional Information for the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation Additional Information for the Transceiver PHY IP Core
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