Altera Transceiver PHY IP Core User Manual
Page 51
Word Addr
Bit
R/W
Name
Description
0x067
[31:0]
RO
pma_rx_is_lockedtoref
When asserted, indicates that the RX
CDR PLL is locked to the reference
clock. Bit <n> corresponds to channel
<n>.
10GBASE-R PCS
0x080
[31:0]
WO
INDIRECT_ADDR
Provides for indirect addressing of all
PCS control and status registers. Use
this register to specify the logical
channel number of the PCS channel
you want to access.
0x081
[2]
RW
RCLR_ERRBLK_CNT
When set to 1, clears the error block
count register. To block: Block
synchronizer
[3]
RW
RCLR_BER_COUNT
When set to 1, clears the bit error rate
(BER) register. To block: BER
monitor
0x082
[0]
R
PCS_STATUS
For Stratix IV devices: When asserted
indicates that the PCS link is up.
[1]
R
HI_BER
When asserted by the BER monitor
block, indicates that the PCS is
recording a high BER. From block:
BER monitor
[2]
R
BLOCK_LOCK
When asserted by the block
synchronizer, indicates that the PCS
is locked to received blocks. From
Block: Block synchronizer
[3]
R
TX_FIFO_FULL
When asserted, indicates the TX FIFO
is full. From block: TX FIFO
[4]
R
RX_FIFO_FULL
When asserted, indicates the RX FIFO
is full. From block: RX FIFO
[5]
R
RX_SYNC_HEAD_ERROR
For Stratix V devices, when asserted,
indicates an RX synchronization
error. This signal is Stratix V devices
only.
[6]
R
RX_SCRAMBLER_ERROR
For Stratix V devices: When asserted,
indicates an RX scrambler error.
[7]
R
RX_DATA_READY
When asserted indicates that the RX
interface is ready to send out received
data. From block: 10 Gbps Receiver
PCS
UG-01080
2015.01.19
10GBASE-R PHY Register Interface and Register Descriptions
3-27
10GBASE-R PHY IP Core
Altera Corporation