Altera Transceiver PHY IP Core - Manual (Page 131)

Figure 5-4: Block Diagram for Reconfiguration Example
1G/10Gb
Ethernet
MAC
Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function
Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function
Backplane-KR or 1G/10Gb Ethernet PHY MegaCore Function
Native PHY Hard IP
257.8
MHz
40-b
40-b
TX
Serial
Data
RX
Serial
Data
322.265625 or
644.53125
Ref Clk
62.5 or 125
Ref Clk
ATX/CMU
TX PLL
For
10 GbE
ATX/CMU
TX PLL
For 1 GbE
1.25 Gb/
10.3125 Gb
Hard PMA
Link
Status
Sequencer S
Reset
Controller
State
Machine
Arbiter
rate change request
ack to user
rate change
req from user
Transceiver
Reconfig
Controller
10 Gb
Ethernet
Hard PCS
Cntl &
Status
RX GMII Data
TX GMII Data
@ 125 MHz
RX XGMII Data
TX XGMII Data
Shared Across Multiple Channels
Can Share
Across Multiple
Channels
@156.25 MHz
1 GIGE
PCS
1G/10Gb
Ethernet
MAC1G/10Gb
Ethernet
MAC
1G
10G
1 Gb
Ethernet
Standard
Hard PCS
1G/10GbE PHY Arbitration Logic Requirements
This topic describes the arbitration functionality that you must implement.
The arbiter should implement the following logic. You can modify this logic based on your system
requirements:
1. Accept requests from the sequencer (if Enable automatic speed detection is turned On in the GUI) .
Prioritize requests to meet system requirements. Requests should consist of the following two buses:
5-22 1G/10GbE PHY Arbitration Logic Requirements
UG-01080
2015.01.19
Altera Corporation 1G/10 Gbps Ethernet PHY IP Core
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