Altera Transceiver PHY IP Core User Manual
Page 175
Signal Name
Direction
Description
tx_parallel_data
Input
When asserted, indicates that
tx_parallel_data
[63:0]
is valid and is ready to be written into the TX
FIFO. When deasserted, indicates that
tx_parallel_
data
is invalid and is not written into the
TX FIFO. This signal is the data valid or write enable
port of the TX FIFO. This input must be synchronized
to the
tx_coreclkin
clock domain.
The Interlaken MAC should gate
tx_parallel_
data
based on
tx_datain_bp<n>
. Or, you
can tie
tx_datain_bp<n>
directly to
tx_parallel_
data<n>[65]
. For Quartus II releases before 12.0, you
must pre-fill the transmit FIFO so this pin must be
1'b1 when
tx_ready
is asserted, but before
tx_sync_
done
is asserted to insert the pre-fill pattern. Do not
use valid data to pre-fill the transmit FIFO. Use the
following Verilog HDL assignment for Quartus II
releases prior to 12.0:
assign tx_parallel_data[65] = (!tx_sync_
done)?1'b1:tx_datain_bp[0];
tx_ready
Output
When asserted, indicates that the TX interface has
exited the reset state and is ready for service. The
tx_
ready
latency for the TX interface is 0. A 0 latency
means that the TX FIFO can accept data on the same
clock cycle that
tx_ready
is asserted. This output is
synchronous to the
phy_mgmt_clk
clock domain. The
Interlaken MAC must wait for
tx_ready
before
initiating data transfer (pre-fill pattern or valid user
data) on any lanes. The TX FIFO only captures input
data from the Interlaken MAC when
tx_ready
and
tx_parallel_data[65]
are both asserted. The
beginning of the pre-fill stage is marked by the
assertion of
tx_ready
, before
tx_sync_done
is
asserted. The pre-fill stage should terminate when
tx_
ready
is high and
tx_sync_done
changes from Logic
0 to Logic 1 state. At this point, TX synchronization is
complete and valid TX data insertion can begin. TX
synchronization is not required for single-lane
variants. Use the following Verilog HDL assignment is
for Quartus versions earlier than 12.0:
assign tx_parallel_data[65] = (!tx_sync_
done)?1'b1:tx_datain_bp[0];
tx_datain_bp
Output
When asserted, indicates that Interlaken TX lane
interface is ready to receive data for transmission. In
7-8
Interlaken PHY Avalon-ST TX Interface
UG-01080
2015.01.19
Altera Corporation
Interlaken PHY IP Core