Altera Transceiver PHY IP Core - Manual (Page 178)

Signal Name Direction Description
rx_parallel_data<n>
[64]
Output
When asserted, indicates that
rx_parallel_data<n>[63:0]
is
valid. When deasserted, indicates the
rx_parallel_data<n>
[63:0]
is invalid. This output is synchronous to the
rx_
coreclkin
clock domain.
The Interlaken PCS implements a gearbox between the PMA
and PCS interface. The
rx_parallel_data<n>[64]
port is
deasserted whenever the gearbox is in the invalid region. The
Interlaken MAC should not read
rx_parallel_data<n>[65,
63:0]
if
rx_parallel_data<n>[64]
is deasserted.
rx_parallel_data<n>
[65]
Output
Indicates whether
rx_parallel_data<n>[63:0]
represents
control or data. When deasserted,
rx_parallel_data<n>
[63:0]
is a data word. When asserted,
rx_paralleldata<n>
[63:0]
is a control word. This output is synchronous to the
rx_
coreclkin
clock domain.
The value of header synchronization bits[65:64] of the
Interlaken word identify whether bits[63:0] are Framing Layer
Control/Burst/IDLE Word or a data word. The value 2’b10
indicating a Framing Layer Control/Burst/IDLE Word is gray
encoded to the value 1’b1 and
rx_parallel_data<n>[65]
is
asserted by the Interlaken Receive PCS. The value 2’b01
indicating data word is gray encoded to the value 1’b0 and
rx_
parallel_data<n>[65]
is deasserted by the Interlaken Receive
PCS. The Framing Layer Control Words (Frame Sync,
Scrambler State, Skip, and Diag) are not discarded but are sent
to the Interlaken MAC for multi-lane alignment and deskew on
the lanes.
rx_parallel_data<n>
[66]
Output
This is an active-high synchronous status signal indicating that
block lock (frame synchronization) and frame lock (metaframe
boundary delineation) have been achieved. The Interlaken
MAC must use this signal to indicate that Metaframe synchro‐
nization has been achieved for this lane. You must use this
rx_
parallel_data[66]
as the primary frame synchronization
status flag and only use the optional
rx_parallel_data[70]
as
the secondary frame synchronization status flag. This output is
synchronous to the rx_coreclkin clock domain.
If the RX PCS FIFO reaches the empty state or is in an empty
state,
rx_parallel_data<n>[66]
Block Lock and Frame Lock
status signals are deasserted in the next clock cycle.
rx_
parallel_data<n>[70]
indicating metaframe lock and
rx_
parallel_data<n>[69]
indicating that the first Interlaken
synchronization word alignment pattern has been received
remain asserted.
UG-01080
2015.01.19
Interlaken PHY Avalon-ST RX Interface 7-11
Interlaken PHY IP Core Altera Corporation
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