Altera Transceiver PHY IP Core - Manual (Page 264)

Register Interface and Register Descriptions
The Avalon-MM PHY management interface provides access to the Low Latency PHY PCS and PMA
registers that control the TX and RX channels, the PMA powerdown, PLL registers, and loopback modes.
The following figure provides a high level view of this hardware.
Figure 10-3: PMA Top-Level Modules
PMA and Light-Weight PCS
Dynamic
Reconfiguration
Native PMA
Control
Channel
Control
S
Avalon-MM
Control
S
S
Low Latency
PHY Controller
Tx Data
to Embedded
Controller
Transceiver
Reconfiguration
Controller
to and from
User Logic
Tx Parallel Data
Rx Data
Rx Parallel Data
M
Avalon-MM
PHY
Mgmt
S
Tx Serial Data
Rx Serial Data
The following table describes the signals in the PHY Management interface:
Table 10-12: Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk
Input Avalon-MM clock input. There is no
frequency restriction for the
phy_mgmt_clk
;
however, if you plan to use the same clock
for the PHY management interface and
transceiver reconfiguration, you must
restrict the frequency range of
phy_mgmt_
clk
to 100–150 MHz to meet the specifica‐
tion for the transceiver reconfiguration
clock.
phy_mgmt_clk_reset
Input Global reset signal. This signal is active high
and level sensitive. This is an asynchronous
signal.
phy_mgmtaddress[8:0]
Input 9-bit Avalon-MM address.
UG-01080
2015.01.19
Register Interface and Register Descriptions 10-17
Low Latency PHY IP Core Altera Corporation
Send Feedback