Altera Transceiver PHY IP Core - Manual (Page 398)

Interfaces
The Native PHY includes several interfaces that are common to all parameterizations.
The Native PHY allows you to enable ports, even for disabled blocks to facilitate dynamic reconfiguration.
The Native PHY uses the following prefixes for port names:
• Standard PCS ports—
tx_std
,
rx_std
The port descriptions use the following variables to represent parameters:
• <n>—The number of lanes
• <p>—The number of PLLs
• <r>—The number of CDR references clocks selected
Common Interface Ports
This section describes the common interface ports for the IP core.
Common interface consists of reset, clock signals, serial interface ports, control and status ports, parallel
data ports, PMA ports and reconfig interface ports.
Figure 13-3: Common Interface Ports
tx_pll_refclk[-1:0]
tx_pma_clkout[-1:0]
rx_pma_clkout[-1:0]
rx_cdr_refclk[-1:0]
Clock Input
& Output Signals
rx_seriallpbken[-1:0]
rx_setlocktodata[-1:0]
rx_setlocktoref[-1:0]
pll_locked[
-1:0]
rx_is_lockedtodata[-1:0]
rx_is_lockedtoref[-1:0]
rx_clkslip[-1:0]
Control &
Status Ports pll_powerdown[
-1:0]
tx_analogreset[-1:0]
tx_digitalreset[-1:0]
rx_analogreset[-1:0]
rx_digitalreset[-1:0]
Resets
QPI
tx_pma_parallel_data[80-1:0]
rx_pma_parallel_data[80-1:0]
tx_parallel_data[44-1:0]
rx_parallel_data[64-1:0]
tx_pma_qpipullup
tx_pma_qpipulldn
tx_pma_txdetectrx
tx_pma_rxfound
rx_pma_qpipulldn
Parallel
Data Ports
tx_serial_data[-1:0]
rx_serial_data[-1:0]
TX & RX
Serial Ports
reconfig_to_xcvr [(70-1):0]
reconfig_from_xcvr [(46-1):0]
tx_cal_busy[-1:0]
rx_cal_busy[-1:0]
Reconfiguration
Interface Ports
Native PHY Common Interfaces
ext_pll_clk[
-1:0]
UG-01080
2015.01.19
Interfaces 13-23
Arria V Transceiver Native PHY IP Core Altera Corporation
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