Altera Transceiver PHY IP Core - Manual (Page 575)

The Quartus II Fitter can merge the TX PLLs for multiple transceiver PHY IP cores under the following
conditions:
• The PLLs connect to the same reset pin.
• The PLLs connect to the same reference clock.
• The PLLs connect to the same Transceiver Reconfiguration Controller.
The following figure illustrates a design where the CMU PLL in channel 1 provides the clock to three
Custom PHY channels and two 10GBASE-R PHY channels.
Figure 16-14: PLL Shared by Multiple Transceiver PHY IP Cores in a Single Transceiver Bank
Transceiver Bank
to Embedded
Processor
Reconfig to
and from
Transceiver
Stratix V GX, GS, or GT Device
S M
3 Transceiver
Channels
Custom
10 GBASE-R
10 GBASE-R
Transceiver
Reconfiguration
Controller
3 Transceiver
Channels
Custom
Custom
CMU PLL
S
S
Sharing Reconfiguration Interface for Multi-Channel Transceiver Designs
Although you must initially create a separate reconfiguration interface for each channel and TX PLL in
your design, when the Quartus II software compiles your design, it reduces the number of reconfiguration
interfaces by merging reconfiguration interfaces. The synthesized design typically includes a reconfigura‐
tion interface for at least three channels because three channels share an Avalon-MM slave interface
which connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you cannot connect
the three channels that share an Avalon-MM interface to different Transceiver Reconfiguration
Controller IP Cores. Doing so causes a Fitter error.
Loopback Modes
The PMA analog registers allow you to enable pre- and post-CDR serial loopback modes.
You can enable the pre- and post-CDR reverse serial loopback modes by writing the appropriate bits of
the Transceiver Reconfiguration Controller
pma_offset
register described in PMA Analog Registers. In
pre-CDR mode, data received through the RX input buffer is looped back to the TX output buffer. In
16-58 Sharing Reconfiguration Interface for Multi-Channel Transceiver Designs
UG-01080
2015.01.19
Altera Corporation Transceiver Reconfiguration Controller IP Core Overview
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