Altera Transceiver PHY IP Core User Manual
Page 677
Date
Document
Version
Changes Made
Transceiver Reconfiguration Controller
April 2013
2.1
Rename table 16-13 to DFE Registers. Fix typo in Reconfig Addr
column changed 7’h11 to 7’h19. In Table 16-8, removed the DCD
Calibration registers row.
Transceiver Reset Controller
April 2013
2.1
No changes from previous release.
Transceiver Reset Controller
April 2013
2.1
No changes from previous release.
Transceiver PLL for Arria V, Arria V GZ, and Stratix V Devices
April 2013
2.1
No changes from previous release.
Analog Parameters Set Using QSF Assignment
April 2013
2.1
Fix typo in the "Analog Settings for Arria V GZ Devices" table.
Migrating from Stratix IV to Stratix V Devices
April 2013
2.1
No changes from previous release.
Date
Document
Version
Changes Made
Introduction
March 2013
2.0
No changes from previous release.
Getting Started
March 2013
2.0
No changes from previous release.
10GBASE-R
March 2013
2.0
No changes from previous release.
10GBASE-KR
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core
21-17
Additional Information for the Transceiver PHY IP Core
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)