Sdc timing constraints, Sdc timing constraints -32 – Altera Transceiver PHY IP Core User Manual
Page 515
Name
Dir
Synchronous to
tx_std_coreclkin/
rx_std_coreclkin
Description
rx_st_wa_patternalign
Input
No
Active when you place the word aligner in
manual mode. In manual mode, you align
words by asserting rx_st_wa_patternalign.
rx_st_wa_patternalign is edge sensitive.
For more information refer to the Word
Aligner section in the Transceiver Architec‐
ture in Cyclone V Devices.
rx_std_wa_a1a2size[
1:0]
Input
No
Used for the SONET protocol. Assert
when the A1 and A2 framing bytes must
be detected. A1 and A2 are SONET
backplane bytes and are only used when
the PMA data width is 8 bits.
rx_std_bitslip[
Input
No
Used when word aligner mode is bitslip
mode. For every rising edge of the
rx_std_
bitslip
signal, the word boundary is
shifted by 1 bit. Each bitslip removes the
earliest received bit from the received data.
You must synchronize this signal.
Miscellaneous
tx_std_elecidle[
Input
When asserted, enables a circuit to detect a
downstream receiver. This signal must be
driven low when not in use because it
causes the TX PMA to enter electrical idle
mode with the TX serial data signals in
tristate mode.
rx_std_signaldetect[
1:0]
Output
No
Signal threshold detect indicator. When
asserted, it indicates that the signal present
at the receiver input buffer is above the
programmed signal detection threshold
value. You must synchronize this signal.
Related Information
SDC Timing Constraints
This section describes SDC timing constraints for the Cyclone V Native PHY.
15-32
SDC Timing Constraints
UG-01080
2015.01.19
Altera Corporation
Cyclone V Transceiver Native PHY IP Core Overview