Altera Transceiver PHY IP Core - Manual (Page 551)

Transceiver Reconfiguration Controller Streamer Module Registers
The Streamer module defines the following two modes for channel and PLL reconfiguration:
• Mode 0—MIF. Uses a memory initialization file (.mif) to reconfigure settings.
• Mode 1—Direct Write. Uses a series of Avalon-MM writes on the reconfiguration management
interface to change settings.
Note: All undefined register bits are reserved.
Table 16-24: Streamer Module Registers
PHY Addr Bits R/W Register Name Description
7’h38 [9:0] RW
logical channel number
The logical channel number. Must be specified
when performing dynamic updates. The
Transceiver Reconfiguration Controller maps
the logical address to the physical address.
7’h3A
[9] R
control and status
Error
. When asserted, indicates an error. This
bit is asserted if any of the following conditions
occur:
• The channel address is invalid.
• The PHY address is invalid.
• The offset register address is invalid.
[8] R
Busy
. When asserted, indicates that a reconfi‐
guration operation is in progress.
[3:2] RW
Mode
. The following encodings are defined:
• 2’b00: MIF. This mode continuously reads
and transfers a .mif file, which contains the
reconfiguration data.
• 2’b01: Direct Write. In this mode, you
specify a logical channel, a register offset,
and data. Depending on the logical channel
specified, the Transceiver Reconfiguration
Controller may mask some of the data
specified to prevent read-only values that
were optimized during startup, from being
over-written. In particular, this mode
protects the following settings:
• Decision feedback equalization controls
• RX buffer offset calibration adjustments
• Duty cycle distortion adjustments
• PMA clock settings
• 2’b10: Reserved
• 2’b11: Reserved
16-34 Transceiver Reconfiguration Controller Streamer Module Registers
UG-01080
2015.01.19
Altera Corporation Transceiver Reconfiguration Controller IP Core Overview
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