Altera Transceiver PHY IP Core - Manual (Page 266)

Word Addr Bits R/W Register Name Description
Reset Control Registers–Automatic Reset Controller
0x063 [31:0] R
pma_rx_signaldetect
When channel =1, indicates that receive
circuit for channel senses the specified
voltage exists at the RX input buffer.
0x064 [31:0] RW
pma_rx_set_
locktodata
When set, programs the RX CDR PLL to
lock to the incoming data. Bit
corresponds to channel .
0x065 [31:0] RW
pma_rx_set_locktoref
When set, programs the RX CDR PLL to
lock to the reference clock. Bit
corresponds to channel .
0x066 [31:0] RO
pma_rx_is_lockedto-
data
When asserted, indicates that the RX CDR
PLL is locked to the RX data, and that the
RX CDR has changed from LTR to LTD
mode. Bit corresponds to channel .
0x067 [31:0] RO
pma_rx_is_
lockedtoref
When asserted, indicates that the RX CDR
PLL is locked to the reference clock. Bit
corresponds to channel .
Dynamic Reconfiguration
As silicon progresses towards smaller process nodes, circuit performance is affected more by variations
due to process, voltage, and temperature (PVT). These process variations result in analog voltages that can
be offset from required ranges. The calibration performed by the dynamic reconfiguration interface
compensates for variations due to PVT.
Each channel and each TX PLL have separate dynamic reconfiguration interfaces. The MegaWizard Plug-
In Manager provides informational messages on the connectivity of these interfaces. The following
example shows the messages for a single duplex channel.
Example 10-1: Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 2 reconfiguration interfaces for connection to the external reconfiguration
controller.
Reconfiguration interface offset 0 is connected to the transceiver channel.
Reconfiguration interface offset 1 is connected to the transmit PLL.
Although you must initially create a separate reconfiguration interface for each channel and TX PLL in
your design, when the Quartus II software compiles your design, it reduces the number of reconfiguration
interfaces by merging reconfiguration interfaces. The synthesized design typically includes a reconfigura‐
tion interface for at least three channels because three channels share an Avalon-MM slave interface
which connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you cannot connect
the three channels that share an Avalon-MM interface to different Transceiver Reconfiguration
UG-01080
2015.01.19
Dynamic Reconfiguration 10-19
Low Latency PHY IP Core Altera Corporation
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