Freescale Semiconductor MPC8260 - Manual (Page 999)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 30-79
Table 30-40 describes AAL0 TxBD fields.
30.10.5.13 AAL1 CES TxBDs
Refer to Section 31.12.2, “AAL1 CES TxBDs
0 1 2 3 4 5 6 7 10 11 12 15
Offset + 0x00 R — W I — CM — OAM —
Offset + 0x02 —
Offset + 0x04 Tx Data Buffer Pointer (TXDBPTR)
Offset + 0x06
Figure 30-52. AAL0 TxBDs
Table 30-40. AAL0 TxBD Field Descriptions
Offset Bits Name Description
0x00 0 R Ready
0 The buffer is not ready for transmission. The user can manipulate this BD or its buffer.
The CP clears R after the buffer has been sent or after an error occurs.
1 The buffer that the user prepared for transmission has not been sent or is being sent.
No fields of this BD may be written by the user once R is set.
1 — Reserved, should be cleared.
2 W Wrap (final BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from
the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The
number of TxBDs in this table is determined by the W bit. The current table is
constrained to 64 Kbytes.
3 I Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.
FCCE[GINT x ] is set when the INT_CNT counter reaches the global interrupt
threshold.
4–5 — Reserved, should be cleared.
6 CM Continuous mode
0 Normal operation.
1 The CP does not clear the ready bit after this BD is closed, allowing the associated
buffer to be retransmitted automatically when the CP next accesses this BD.
7–10 — Reserved, should be cleared.
11 OAM Operation and maintenance cell. If OAM is set, the current AAL0 buffer contains an F5
or F4 OAM cell. Performance monitoring calculations are not done on OAM cells.
11–15 — Reserved, should be cleared.
0x02 — — Reserved, should be cleared.
0x04 — TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or may
not be 8-byte-aligned. The buffer may reside in either internal or external memory. This
value is not modified by the CP.