Freescale Semiconductor MPC8260 - Manual (Page 15)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xiii
Contents
Paragraph
Number
Title
Page
Number
9.11.1.5 PCI Outbound Comparison Mask Registers (POCMRx) ..................................... 9-31
9.11.1.6 Discard Timer Control Register (PTCR) .............................................................. 9-32
9.11.1.7 General Purpose Control Register (GPCR) .......................................................... 9-33
9.11.1.8 PCI General Control Register (PCI_GCR) ........................................................... 9-35
9.11.1.9 Error Status Register (ESR) .................................................................................. 9-35
9.11.1.10 Error Mask Register (EMR) ................................................................................. 9-37
9.11.1.11 Error Control Register (ECR) ............................................................................... 9-38
9.11.1.12 PCI Error Address Capture Register (PCI_EACR) .............................................. 9-39
9.11.1.13 PCI Error Data Capture Register (PCI_EDCR) .................................................... 9-40
9.11.1.14 PCI Error Control Capture Register (PCI_ECCR) ............................................... 9-40
9.11.1.15 PCI Inbound Translation Address Registers (PITARx) ........................................ 9-42
9.11.1.16 PCI Inbound Base Address Registers (PIBARx) .................................................. 9-42
9.11.1.17 PCI Inbound Comparison Mask Registers (PICMRx) ........................................ 9-43
9.11.2 PCI Bridge Configuration Registers ........................................................................ 9-45
9.11.2.1 Vendor ID Register ............................................................................................... 9-46
9.11.2.2 Device ID Register ............................................................................................... 9-47
9.11.2.3 PCI Bus Command Register ................................................................................. 9-47
9.11.2.4 PCI Bus Status Register ........................................................................................ 9-48
9.11.2.5 Revision ID Register ............................................................................................. 9-49
9.11.2.6 PCI Bus Programming Interface Register ............................................................ 9-50
9.11.2.7 Subclass Code Register ......................................................................................... 9-50
9.11.2.8 PCI Bus Base Class Code Register ....................................................................... 9-51
9.11.2.9 PCI Bus Cache Line Size Register ....................................................................... 9-51
9.11.2.10 PCI Bus Latency Timer Register .......................................................................... 9-52
9.11.2.11 Header Type Register ........................................................................................... 9-52
9.11.2.12 BIST Control Register .......................................................................................... 9-53
9.11.2.13 PCI Bus Internal Memory-Mapped Registers Base Address
Register (PIMMRBAR) .................................................................................... 9-53
9.11.2.14 General Purpose Local Access Base Address Registers (GPLABARx) .............. 9-54
9.11.2.15 Subsystem Vendor ID Register ............................................................................. 9-55
9.11.2.16 Subsystem Device ID Register ............................................................................. 9-56
9.11.2.17 PCI Bus Capabilities Pointer Register .................................................................. 9-56
9.11.2.18 PCI Bus Interrupt Line Register ........................................................................... 9-56
9.11.2.19 PCI Bus Interrupt Pin Register ............................................................................. 9-57
9.11.2.20 PCI Bus MIN GNT ............................................................................................... 9-57
9.11.2.21 PCI Bus MAX LAT .............................................................................................. 9-58
9.11.2.22 PCI Bus Function Register ................................................................................... 9-58
9.11.2.23 PCI Bus Arbiter Configuration Register ............................................................... 9-59
9.11.2.24 PCI Hot Swap Register Block .............................................................................. 9-60
9.11.2.25 PCI Hot Swap Control Status Register ................................................................. 9-61
9.11.2.26 PCI Configuration Register Access from the Core ............................................... 9-62