Freescale Semiconductor MPC8260 - Manual (Page 24)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
xxii Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
19.5.2 Memory to/from Peripheral Transfers ....................................................................... 19-9
19.5.2.1 Dual-Address Transfers ....................................................................................... 19-10
19.5.2.1.1 Peripheral to Memory ...................................................................................... 19-10
19.5.2.1.2 Memory to Peripheral ...................................................................................... 19-10
19.5.2.2 Single Address (Fly-By) Transfers ...................................................................... 19-10
19.5.2.2.1 Peripheral-to-Memory Fly-By Transfers ......................................................... 19-11
19.5.2.2.2 Memory-to-Peripheral Fly-By Transfers ......................................................... 19-11
19.5.3 Controlling 60x Bus Bandwidth .............................................................................. 19-11
19.5.4 PCI Burst Length and Latency Control ................................................................... 19-12
19.6 IDMA Priorities ........................................................................................................... 19-13
19.7 IDMA Interface Signals ............................................................................................... 19-13
19.7.1 DREQx and DACKx ............................................................................................... 19-13
19.7.1.1 Level-Sensitive Mode .......................................................................................... 19-14
19.7.1.2 Edge-Sensitive Mode........................................................................................... 19-15
19.7.2 DONEx .................................................................................................................... 19-15
19.8 IDMA Operation .......................................................................................................... 19-16
19.8.1 Auto Buffer and Buffer Chaining ............................................................................ 19-16
19.8.2 IDMAx Parameter RAM ......................................................................................... 19-17
19.8.2.1 DMA Channel Mode (DCM)............................................................................... 19-19
19.8.2.2 Data Transfer Types as Programmed in DCM..................................................... 19-21
19.8.2.3 Programming DTS and STS ................................................................................ 19-22
19.8.3 IDMA Performance ................................................................................................. 19-23
19.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR) .................................... 19-24
19.8.5 IDMA BDs............................................................................................................... 19-24
19.9 IDMA Commands........................................................................................................ 19-27
19.9.1 start_idma Command............................................................................................... 19-27
19.9.2 stop_idma Command ............................................................................................... 19-28
19.10 IDMA Bus Exceptions ................................................................................................. 19-28
19.10.1 Externally Recognizing IDMA Operand Transfers ................................................. 19-29
19.11 Programming the Parallel I/O Registers ...................................................................... 19-29
19.12 IDMA Programming Examples ................................................................................... 19-30
19.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)—IDMA2 ............................ 19-30
19.12.2 Memory-to-Peripheral Fly-By Mode—IDMA3 ...................................................... 19-32
19.12.3 Memory-to-Memory (PCI Bus to 60x Bus)—IDMA1 ............................................ 19-33
Chapter 20
Serial Communications Controllers (SCCs)
20.1 Features .......................................................................................................................... 20-2
20.1.1 The General SCC Mode Registers (GSMR1–GSMR4) ............................................ 20-3
20.1.2 Protocol-Specific Mode Register (PSMR) ................................................................ 20-9