Freescale Semiconductor MPC8260 - Manual (Page 1339)

Index I–I
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor Index-11
accessing the bus, 22-18
bus controller, 22-16
collision detection, 22-16, 22-19
commands, 22-5
delayed RTS mode, 22-20
error handling, 22-5
fast communications controllers (FCCs)
bit stuffing, 36-1
error control, 36-1
error handling, 36-6
FCCE, 36-14
FCCM, 36-14
FCCS, 36-16
features list, 36-1
FPSMR, 36-7
frame reception, 36-3
frame transmission, 36-2
overview, 36-1
parameter RAM, 36-3
programming model, 36-5
receive commands, 36-6
reception errors, 36-6
RxBD, 36-9
transmission errors, 36-6
transmit commands, 36-5
TxBD, 36-12
features list, 22-1
GSMR, HDLC bus protocol programming, 22-22
multi-master bus configuration, 22-17
overview, 22-1
parameter RAM, 22-3
performance, increasing, 22-19
programming example, 22-14, 22-22
programming the controller, 22-4
PSMR, 22-7
RxBD, 22-8
single-master bus configuration, 22-18
TxBD, 22-11
using the TSA, 22-21
HID0 register
bit settings, 2-11
doze, nap, sleep, DPM bits, 2-12
I
I2ADD (I
2
C address) register, 39-6
I2BRG (I
2
C baud rate generator) register, 39-7
I
2
C controller
block diagram, 39-1
BRGCLK, 39-2
clocking and pin functions, 39-2
commands, 39-11
features list, 39-2
loopback testing, 39-4
master read (slave write), 39-4
master write (slave read), 39-3
multi-master considerations, 39-5
parameter RAM, 39-9
programming model, 39-6
registers, 39-6
RxBD, 39-12
slave read (master write), 39-3
slave write (master read), 39-4
transfers, 39-2
TxBD, 39-13
I2C memory map,, 3-16
I2CER (I
2
C event register), 39-7
I2CMR (I
2
C mask register), 39-7
I2COM (I
2
C command) register, 39-8
I2MOD (I
2
C mode) register, 39-6
IDL interface programming,, 15-29
IDL interface support, 15-25
IDMA emulation
auto buffer, 19-16
buffer chaining, 19-16
buffers, 19-24
bus exceptions, 19-28
commands, 19-27
controlling 60x bus bandwidth, 19-11
DACKx, 19-13
DCM, 19-19
DONEx, 19-15
DREQx, 19-13
DTS/STS programming, 19-22
dual-address transfers, 19-10
edge-sensitive mode, 19-15
exception, bus, 19-28
external request mode, 19-8
features list, 19-5
IDMR, 19-24
IDSR, 19-24
level-sensitive mode, 19-14
normal mode, 19-9
operand transfers, recognizing, 19-29
operation, 19-16
overview, 19-5
parallel I/O register programming, 19-29
parameter RAM, 19-17
priorities, 19-13
programming examples, 19-30
programming the parallel I/O registers, 19-29
signals, 19-13
single address transfers (fly-by), 19-10
transfers, 19-6
IDMA parameter RAM,, 19-17