Freescale Semiconductor MPC8260 - Manual (Page 740)

SCC HDLC Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
22-12 Freescale Semiconductor
The data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).”
22.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
The SCC event register (SCCE) is used as the HDLC event register to report events recognized by the
HDLC channel and to generate interrupts. When an event is recognized, the SCC sets the corresponding
SCCE bit. Interrupts generated through SCCE can be masked in the SCC mask register (SCCM) which has
the same bit format as the SCCE. Setting an SCCM bit enables the corresponding interrupt; clearing a bit
masks it. SCCE bits are cleared by writing ones; writing zeros has no effect. All unmasked bits must be
cleared before the CP clears the internal interrupt request.
Figure 22-7 shows SCCE/SCCM for HDLC
operation.
Table 22-9 describes SCCE/SCCM fields.
0 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field — DCC FLG IDL GRA — TXE RXF BSY TXB RXB
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0x11A10 (SCCE1); 0x0x11A30 (SCCE2); 0x0x11A50 (SCCE3); 0x0x11A70 (SCCE4)
0x0x11A14 (SCCM1); 0x0x11A34 (SCCM2); 0x0x11A54 (SCCM3); 0x0x11A74 (SCCM4)
Figure 22-7. HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)
Table 22-9. SCCE/SCCM Field Descriptions
1
Bits Name Description
0–4 — Reserved, should be cleared. Refer to note 1 below.
5 DCC DPLL carrier sense changed. Set when the carrier sense status generated by the DPLL changes.
Real-time status can be read in SCCS[CS]. This is not the CD status reported in port C. Valid only when
the DPLL is used.
6 FLG Flag status. Set when the SCC stops or starts receiving HDLC flags. Real-time status can be read in
SCCS[FG].
7 IDL Idle sequence status changed. Set when HDLC line status changes. Real-time status of the line can be
read in SCCS[ID].
8 GRA Graceful stop complete. A GRACEFUL STOP TRANSMIT command completed execution. Set as soon as the
transmitter has sent a frame in progress when the command was issued. Set immediately if no frame
was in progress when the command was issued.
9–10 — Reserved, should be cleared. Refer to note 1 below.
11 TXE Tx error. Indicates an error (CTS lost or underrun) has occurred on the transmitter channel.
12 RXF Rx frame. Set when the number of receive frames specified in RFTHR are received on the HDLC
channel. It is set no sooner than two clocks after the last bit of the closing flag is received. This event is
not maskable via the RxBD[I] bit.
13 BSY Busy condition. Indicates a frame arrived but was discarded due to a lack of buffers.