Freescale Semiconductor MPC8260 - Manual (Page 732)

SCC HDLC Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
22-4 Freescale Semiconductor
Figure 22-2 shows 16- and 8-bit address recognition.
Figure 22-2. HDLC Address Recognition
22.5 Programming the SCC in HDLC Mode
HDLC mode is selected for an SCC by writing GSMR_L[MODE] = 0b0000. The HDLC controller
uses the same buffer and BD data structure as other modes and supports multibuffer operation and
0x46 MFLR Hword Max frame length register. The HDLC compares the incoming HDLC frame’s length
with the user-defined limit in MFLR. If the limit is exceeded, the rest of the frame is
discarded and RxBD[LG] is set in the last BD of that frame. At the end of the frame
the SCC reports frame status and frame length in the last RxBD. The MFLR is
defined as all in-frame bytes between the opening and closing flags.
0x48 MAX_CNT Hword Maximum length counter. A temporary down-counter used to track frame length.
0x4A RFTHR Hword Received frames threshold. Used to reduce potential interrupt overhead when each
in a series of short HDLC frames causes an SCCE[RXF] event. Setting RFTHR
determines the frequency of RXF interrupts, which occur only when the RFTHR
limit is reached. Provide enough empty RxBDs for the number of frames specified
in RFTHR.
0x4C RFCNT Hword Received frames count. RFCNT is a down-counter used to implement RFTHR.
0x4E HMASK Hword Mask register (HMASK) and four address registers (HADDR n ) for address
recognition. The SCC reads the frame address from the HDLC receiver, compares
it with the HADDRs, and masks the result with HMASK. Setting an HMASK bit
enables the corresponding comparison bit, clearing a bit masks it. When a match
occurs, the frame address and data are written to the buffers. When no match
occurs and a frame is error-free, the nonmatching address received counter
(NMARC) is incremented.
The eight low-order bits of HADDR
n should contain the first address byte after the
opening flag. For example, to recognize a frame that begins 0x7E (flag), 0x68,
0xAA, using 16-bit address recognition, HADDR
n should contain 0xAA68 and
HMASK should contain 0xFFFF. For 8-bit addresses, clear the eight high-order
HMASK bits. See
Figure 22-2 .
0x50 HADDR1 Hword
0x52 HADDR2 Hword
0x54 HADDR3 Hword
0x56 HADDR4 Hword
0x58 TMP Hword Temporary storage.
0x5A TMP_MB Hword Temporary storage.
1 From SCC base. See Section 20.3.1, “SCC Base Addresses .”
Table 22-1. HDLC-Specific SCC Parameter RAM Memory Map (continued)
Offset 1 Name Width Description
Flag
0x7E
etc.
Flag
0x7E
Address
0x68
Address
0xAA
Control
0x44
etc.
Address
0x55
Control
0x44
16-Bit Address Recognition 8-Bit Address Recognition
0x00FF HMASK
0xXX55 HADDR1
0xXX55 HADDR2
0xXX55 HADDR3
0xXX55 HADDR4
0xFFFF HMASK
0xAA68 HADDR1
0xFFFF HADDR2
0xAA68 HADDR3
0xAA68 HADDR4
Recognizes one 16-bit address (HADDR1) and
the 16-bit broadcast address (HADDR2)
Recognizes a single 8-bit address (HADDR