Freescale Semiconductor MPC8260 - Manual (Page 673)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 19-29
19.10.1 Externally Recognizing IDMA Operand Transfers
The following ways can be used determine externally that the IDMA is executing a bus transaction:
• The TC[2] signal (programmed in DCM[TC2]) or SDMA channels can be programmed to a unique
code that identifies an IDMA transfer.
• The DACK signal shows accesses to the peripheral device. DACK activates on either the source
or destination bus transactions, depending on DCM[S/D].
19.11 Programming the Parallel I/O Registers
The parallel I/O registers control the use of the external pins of the chip. Each pin can be used for different
purposes. See
Table 19-12 , Table 19-13 and Table 19-14 (optional) for the proper parallel I/O register
programming dedicating the proper external ports to the four IDMA channels’ external I/O signals.
Each port is controlled by five I/O registers: PPAR, PSOR, PDIR, PODR, and PDAT. Each bit in these
registers controls the external pin of the same location.
• PPARC selects the pins general purpose(0)/dedicated(1) mode for port C.
• PDIRC select the pins input or inout (0)/output(1) mode for port C.
• PODRC selects the open drain pins for port C.
• PSORC selects the pins dedicated1(0)/dedicated2(1) mode for port C.
• PPARA, PDIRA, PODRA, and PSORA control port A in the same way.
• PPARD, PDIRD, PODRD, and PSORD control port D in the same way.
• The default is the value that is seen by the IDMA channel on the pin (input or inout mode
only—PDIR[PN] = 0) if a PSORx register bit is set to the complement value of the value in
Table 19-12 , Table 19-13 and Table 19-14 . See Section 40.2, “Port Registers.”
Table 19-13 describes parallel I/O register programming for port A.
Table 19-12. Parallel I/O Register Programming—Port C
Channel Signal Pin PPARC PDIRC PODRC PSORC Default
IDMA1 DREQ1 (I) PC[0] 1 0 0 0 GND
DACK1 (O) PC[23] 1 1 0 1 —
DONE1 (I/O) PC[22] 1 0 1 1 VDD
IDMA2 DREQ2 (I) PC[1] 1 0 0 0 GND
DACK2 (O) PC[3] 1 1 0 1 —
DONE2 (I/O) PC[2] 1 0 1 1 VDD