Freescale Semiconductor MPC8260 - Manual (Page 485)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-67
11.6.1.3 Software Requests— RUN Command
Software can start a request to the UPM by issuing a RUN command to the UPM. Some memory devices
have their own signal handshaking protocol to put them into special modes, such as self-refresh mode.
Other memory devices require special commands to be issued on their control signals, such as for SDRAM
initialization.
For these special cycles, the user creates a special RAM pattern that can be stored in any unused areas in
the UPM RAM. Then the
RUN command is used to run the cycle. The UPM runs the pattern beginning at
the specified RAM location until it encounters a RAM word with its LAST bit set. The RUN command is
issued by setting MxMR[OP] = 11 and accessing the UPMx memory region with a single-byte transaction.
Note that the pattern must contain exactly one assertion of PSDVAL (UTA bit in the RAM word, described
in Table 11-36.), otherwise bus timeout may occur.
11.6.1.4 Exception Requests
When the PowerQUICC II under UPM control initiates an access to a memory device, the external device
may assert TEA or SRESET. The UPM provides a mechanism by which memory control signals can meet
the timing requirements of the device without losing data. The mechanism is the exception pattern that
defines how the UPM deasserts its signals in a controlled manner.
11.6.2 Programming the UPMs
The UPM is a microsequencer that requires microinstructions or RAM words to generate signal timings
for different memory cycles. Follow these steps to program the UPMs:
1. Set up BRx and ORx.
2. Write patterns into the RAM array.
3. Program MPTPR and L/PURT if refresh is required.
4. Program the machine mode register (MxMR).
Patterns are written to the RAM array by setting MxMR[OP] = 01 and accessing the UPM with a single
byte transaction. See Figure 11-11..
11.6.3 Clock Timing
Fields in the RAM word specify the value of the various external signals at each clock edge. The signal
timing generator causes external signals to behave according to the timing specified in the current RAM
word.
Figure 11-58 and Figure 11-59 show the clock schemes of the UPMs in the memory controller for
integer and non-integer clock ratios. The clock phases shown reflect timing windows during which
generated signals can change state. If specified in the RAM, the value of the external signals can be
changed after any of the positive edges of T[1–4], plus a circuit delay time as specified in the Hardware
Specifications.