Freescale Semiconductor MPC8260 - Manual (Page 681)

Serial Communications Controllers (SCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 20-3
• Fully transparent option for one half of an SCC (Rx/Tx) while another protocol executes on the
other half (Tx/Rx)
• Echo and local loopback modes for testing
20.1.1 The General SCC Mode Registers (GSMR1–GSMR4)
Each SCC contains a general SCC mode register (GSMR) that defines options common to most of the
protocols. GSMR_L contains the low-order 32 bits; GSMR_H, shown in
Figure 20-2 , contains the
high-order 32 bits. Some GSMR operations are described in later sections.
Table 20-1 describes GSMR_H fields.
0 14 15
Field —
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x0x11A04 (GSMR1); 0x0x11A24 (GSMR2); 0x0x11A44 (GSMR3); 0x0x11A64 (GSMR4)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field TCRC REVD TRX TTX CDP CTSP CDS CTSS TFL RFW TXSY SYNL RTSM RSYN
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11A06 (GSMR1); 0x11A26 (GSMR2); 0x11A46 (GSMR3); 0x11A66 (GSMR4)
Figure 20-2. GSMR_H—General SCC Mode Register (High Order)
Table 20-1. GSMR_H Field Descriptions
Bit Name Description
0–15 — Reserved, should be cleared.
16–17 TCRC Transparent CRC (valid for totally transparent channel only). Selects the frame checking provided
on transparent channels of the SCC (either the receiver, transmitter, or both, as defined by TTX and
TRX). Although this configuration selects a frame check type, the decision to send the frame check
is made in the TxBD. Thus, frame checks are not needed in transparent mode and frame check
errors generated on the receiver can be ignored.
00 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1).
01 CRC16 (BISYNC). (X16 + X15 + X2 + 1).
10 32-bit CCITT CRC (Ethernet and HDLC).
(X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + 1).
11 Reserved.
18 REVD Reverse data (valid for a totally transparent channel only)
0 Normal operation.
1 Reverses the bit order for totally transparent channels on this SCC (either the receiver,
transmitter, or both) and sends the msb of each byte first. Section 23.11, “BISYNC Mode Register
(PSMR) ,” describes reversing bit order in a BISYNC protocol.