Freescale Semiconductor MPC8260 - Manual (Page 76)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
lxxiv Freescale Semiconductor
Tables
Table
Number
Title
Page
Number
33-9 ICP Cell Template .............................................................................................................. 33-33
33-10 IMA Group Receive Table Entry ....................................................................................... 33-36
33-11 IGRCNTL Field Descriptions ............................................................................................. 33-39
33-12 IGRSTATE Field Descriptions............................................................................................ 33-39
33-13 IRGFS Field Descriptions ................................................................................................... 33-40
33-14 Receive Group Order Table Entry Field Descriptions ........................................................ 33-41
33-15 IMA Link Transmit Table Entry ........................................................................................ 33-41
33-16 ILTCNTL Field Descriptions .............................................................................................. 33-42
33-17 ILTSTATE Field Descriptions............................................................................................. 33-43
33-18 ITINTSTAT Field Descriptions........................................................................................... 33-44
33-19 IMA Link Receive Table Entry........................................................................................... 33-44
33-20 ILRCNTL Field Descriptions ............................................................................................. 33-46
33-21 ILRSTATE Field Descriptions ............................................................................................ 33-47
33-22 IMA Link Receive Statistics Table Entry ........................................................................... 33-48
33-23 IMA Interrupt Queue Entry Field Descriptions .................................................................. 33-51
33-24 Unavailable Features when DREQx used as IDCR Master Clock ..................................... 33-53
33-25 IDCR IMA Root Parameters............................................................................................... 33-54
33-26 IDCR Table Entry ............................................................................................................... 33-54
33-27 IDSR/IDMR Field Descriptions.......................................................................................... 33-55
33-28 Examples of APC Programming for IMA .......................................................................... 33-56
33-29 COMM_INFO Field Descriptions ...................................................................................... 33-58
34-1 TC Layer Signals .................................................................................................................. 34-7
34-2 TCMODEx Field Descriptions ............................................................................................. 34-8
34-3 CDSMRx Field Descriptions ................................................................................................ 34-9
34-4 TCERx Field Descriptions .................................................................................................. 34-10
34-5 TCGER Field Descriptions ................................................................................................ 34-11
34-6 TCGSR Field Descriptions ................................................................................................. 34-12
34-7 Programming GFMR and FPSMR to Setup the FCC2 ....................................................... 34-17
34-8 Enable FCC2 ....................................................................................................................... 34-17
34-9 Programming the CPM MUX for a TI Application ............................................................ 34-17
34-10 Programming the TC Layer Block...................................................................................... 34-17
34-11 Programming the SI RAM (Rx or Tx) for a T1 Application .............................................. 34-18
34-12 Programming SI Registers to Enable TDM ........................................................................ 34-18
35-1 Flow Control Frame Structure .............................................................................................. 35-7
35-2 Ethernet-Specific Parameter RAM ....................................................................................... 35-8
35-3 Transmit Commands ........................................................................................................... 35-12
35-4 Receive Commands............................................................................................................ 35-12
35-5 RMON Statistics and Counters ........................................................................................... 35-13
35-6 Transmission Errors ............................................................................................................ 35-18
35-7 Reception Errors ................................................................................................................. 35-18
35-8 FPSMR Ethernet Field Descriptions................................................................................... 35-19