Freescale Semiconductor MPC8260 - Manual (Page 386)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-80 Freescale Semiconductor
Figure 9-76. Outbound Message Interrupt Mask Register (OMIMR)
Table 9-61 describes OMIMR fields.
9.12.3.4.5 Inbound Message Interrupt Status Register (IMISR)
This register contains the interrupt status of the I
2
O, door bell, and message register events. Writing a 1 to
the corresponding set bit will clear the bit. The events are generated by the PCI masters. IMISR should be
accessed only from the 60x bus and only in agent mode. Accesses while in host mode or from the PCI bus
have undefined results.
31 16
Field —
Reset 0000_0000_0000_0000
R/W Refer to Table 9-61 .
Addr 0x10436
15 6 5 4 3 2 1 0
Field — OPQIM — ODIM — OM1IM OM0IM
Reset 0000_0000_0000_0000
R/W Refer to Table 9-61 .
Addr 0x10434
Table 9-61. OMIMR Field Descriptions
Bits Name R/W Description
31–6 — R Reserved, should be cleared.
5 OPQIM RW Outbound post queue interrupt mask
0 Outbound post queue interrupt is allowed.
1 Outbound post queue interrupt is masked.
4 — R Reserved, should be cleared.
3 ODIM RW Outbound doorbell interrupt mask
0 Outbound doorbell interrupt is allowed.
1 Outbound doorbell interrupt is masked.
2 — R Reserved, should be cleared.
1 OM1IM RW Outbound message 1 interrupt mask
0 Outbound message 1 interrupt is allowed.
1 Outbound message 1 interrupt is masked.
0 OM0IM RW Outbound message 0 interrupt mask
0 Outbound message 0 interrupt is allowed.
1 Outbound message 0 interrupt is masked.