Freescale Semiconductor MPC8260 - Manual (Page 62)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
lx Freescale Semiconductor
Figures
Figure
Number
Title
Page
Number
33-23 IMA Transmit Interrupt Status (ITINTSTAT)..................................................................... 33-43
33-24 IMA Link Receive Control (ILRCNTL)............................................................................. 33-46
33-25 IMA Link Receive State (ILRSTATE)................................................................................ 33-47
33-26 IMA Transmit Queue .......................................................................................................... 33-48
33-27 Cell Buffer in Delay Compensation Buffer......................................................................... 33-49
33-28 IMA Delay Compensation Buffer ....................................................................................... 33-49
33-29 IMA Interrupt Queue Entry................................................................................................. 33-50
33-30 IDMA Event/Mask Registers in IDCR Mode (IDSR/IDMR) ............................................ 33-55
33-31 COMM_INFO Field ........................................................................................................... 33-58
33-32 IMA Microcode/Software Interaction................................................................................. 33-59
33-33 Near-End versus Far-End .................................................................................................... 33-65
34-1 Serial ATM Using FCC2 and TC Blocks (Single Channel).................................................. 34-1
34-2 TC Layer Block Diagram...................................................................................................... 34-4
34-3 TC Cell Delineation State Machine ...................................................................................... 34-5
34-4 HEC: Receiver Modes of Operation ..................................................................................... 34-6
34-5 TC Layer Mode Register (TCMODEx) ................................................................................ 34-8
34-6 Cell Delineation State Machine Register (CDSMRx) .......................................................... 34-9
34-7 TC Layer Event Register (TCERx)..................................................................................... 34-10
34-8 TC Layer General Event Register (TCGER) ...................................................................... 34-11
34-9 TC Layer General Status Register (TCGSR) ...................................................................... 34-12
34-10 TC Operation in FCC External Rate Mode......................................................................... 34-14
34-11 TC Operation in FCC Internal Rate Mode (Sub Rate Mode) ............................................. 34-15
34-12 Example of Serial ATM Application .................................................................................. 34-16
35-1 Ethernet Frame Structure ...................................................................................................... 35-1
35-2 Ethernet Block Diagram ....................................................................................................... 35-2
35-3 Connecting the PowerQUICC II to Ethernet ........................................................................ 35-4
35-4 Ethernet Address Recognition Flowchart ........................................................................... 35-16
35-5 FCC Ethernet Mode Registers (FPSMR)............................................................................ 35-19
35-6 Ethernet Event Register (FCCE)/Mask Register (FCCM).................................................. 35-20
35-7 Ethernet Interrupt Events Example ..................................................................................... 35-22
35-8 Fast Ethernet Receive Buffer (RxBD) ................................................................................ 35-23
35-9 Ethernet Receiving Using RxBDs....................................................................................... 35-25
35-10 Fast Ethernet Transmit Buffer (TxBD) ............................................................................... 35-26
36-1 HDLC Framing Structure...................................................................................................... 36-2
36-2 HDLC Address Recognition Example .................................................................................. 36-5
36-3 HDLC Mode Register (FPSMR)........................................................................................... 36-8
36-4 FCC HDLC Receiving Using RxBDs................................................................................. 36-10
36-5 FCC HDLC Receive Buffer Descriptor (RxBD) ................................................................ 36-11
36-6 FCC HDLC Transmit Buffer Descriptor (TxBD) ............................................................... 36-12
36-7 HDLC Event Register (FCCE)/Mask Register (FCCM) .................................................... 36-14
36-8 HDLC Interrupt Event Example ......................................................................................... 36-16