Freescale Semiconductor MPC8260 - Manual (Page 1354)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-26 Freescale Semiconductor
U–U Index
TESCRx (60x bus error status and control registers), 4-38,
11-33
TFCR (Tx buffer function code register)
overview, 20-15
TGCR (timer global configuration registers), 18-3
Timers
block diagram, 18-1
bus monitoring, 18-3
cascaded mode block diagram, 18-3
features, 18-1
general-purpose units, 18-2
pulse measurement, 18-3
Time-slot assigner
connecting to the TSA, 15-7
Time-slot assigner (TSA)
synchronization in transparent mode, 24-5
Timing
SCC timing, controlling, 20-17
TM_CMD (RISC timer command) register, 14-24
TMCNT (time counter register), 4-44
TMCNTAL (time counter alarm register), 4-45
TMCNTSC (time counter status and control register), 4-44
TMR (timer mode registers), 18-5
TODR (transmit-on-demand register)
AppleTalk mode, 26-4
overview, 20-10
TOSEQ (transmit out-of-sequence) register, 21-9
Transmission convergence (TC) layer, 34-1
Transparent mode
achieving synchronization, 24-3
commands, 24-6
DSR receiver SYNC pattern lengths, 24-3
end of frame detection, 24-5
error handling, 24-7
fast communications controllers (FCCs)
features list, 37-1
receive operation, 37-2
synchronization
achieving, 37-2
example, 37-3
external signals, 37-3
in-line pattern, 37-2
transmit operation, 37-2
frame reception, 24-2
frame transmission, 24-2
inherent synchronization, 24-5
in-line synchronization, 24-5
overview, 24-1
programming example, 24-12
RxBD, 24-8
serial management controllers (SMCs)
features list, 27-20
overview, 27-20
parameter RAM, 27-6
reception process, 27-21
synchronization signals, 24-3
synchronization, user-controlled, 24-5
transmit synchronization, 24-3
TxBD, 24-10
TRR (timer reference registers), 18-6
TSIZn (transfer size) signals, 8-12
TSTATE (internal transmitter state) register, 28-7
TTn (transfer type) signals, 8-9
U
UART mode
commands, 21-6
control character insertion, 21-9
data handling, character and message-based, 21-5
error reporting, 21-5
features list, 21-2
fractional stop bits, 21-10
handling errors, 21-11
hunt mode, 21-9
normal asynchronous mode, 21-2
overview, 21-1
parameter RAM, 21-3
programming example, 21-22
RxBD, 21-14
serial management controllers
character mode, 27-11
commands, 27-12
data handling, 27-11
error handling, 27-13
features list, 27-11
features not supported by SMCs, 27-10
frame format, 27-10
message-oriented mode, 27-11
overview, 27-10
parameter RAM, 27-6
programming example, 27-19
reception process, 27-11
RxBD, 27-13
transmission process, 27-11
TxBD, 27-17
S-records loader application, 21-23
status reporting, 21-5
synchronous mode, 21-3
TxBD, 21-18
UPMs (user-programmable machines)
access times, handling devices, 11-101
address control bits, 11-77
address mulitplexing, 11-77
clock timing, 11-67