Freescale Semiconductor MPC8260 - Manual (Page 148)

Memory Map
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
3-2 Freescale Semiconductor
0x10029 Reserved — 24 bits — —
0x1002C 60x bus arbitration-level register high (first 8 clients)
(PPC_ALRH) R/W 32 bits 0x0126_3457 4.3.2.3/4-30
0x10030 60x bus arbitration-level register low (next 8 clients)
(PPC_ALRL) R/W 32 bits 0x89AB_CDEF 4.3.2.3/4-30
0x10034 Local arbiter configuration register (LCL_ACR) R/W 8 bits 0x02 4.3.2.4/4-31
0x10035 Reserved — 24 bits — —
0x10038 Local arbitration-level register (first 8 clients) (LCL_ALRH) R/W 32 bits 0x0126_3457 4.3.2.5/4-32
0x1003C Local arbitration-level register (next 8 clients) (LCL_ALRL) R/W 32 bits 0x89AB_ CDEF 4.3.2.3/4-30
0x10040 60x bus transfer error status control register 1 (TESCR1) R/W 32 bits 0x0000_0000 4.3.2.10/4-38
0x10044 60x bus transfer error status control register 2 (TESCR2) R/W 32 bits 0x0000_0000 4.3.2.11/4-40
0x10048 Local bus transfer error status control register 1
(L_TESCR1) R/W 32 bits 0x0000_0000 4.3.2.12/4-42
0x1004C Local bus transfer error status control register 2
(L_TESCR2) R/W 32 bits 0x0000_0000 4.3.2.13/4-43
0x10050 60x bus DMA transfer error address (PDTEA) R 32 bits undefined 19.2.3/19-4
0x10054 60x bus DMA transfer error MSNUM (PDTEM) R 8 bits undefined 19.2.4/19-4
0x10055 Reserved — 24 bits — —
0x10058 Local bus DMA transfer error address (LDTEA) R 32 bits undefined 19.2.3/19-4
0x1005C Local bus DMA transfer error MSNUM (LDTEM) R 8 bits undefined 19.2.4/19-4
0x1005D–
0x100FF
Reserved — 163
bytes
— —
Memory Controller
0x10100 Base register bank 0 (BR0) R/W 32 bits see Figure 11-6 11.3.1/11-13
0x10104 Option register bank 0 (OR0) R/W 32 bits 0xFE00_0EF4 11.3.2/11-15
0x10108 Base register bank 1 (BR1) R/W 32 bits 0x0000_0000 11.3.1/11-13
0x1010C Option register bank 1 (OR1) R/W 32 bits undefined 11.3.2/11-15
0x10110 Base register bank 2 (BR2) R/W 32 bits 0x0000_0000 11.3.1/11-13
0x10114 Option register bank 2 (OR2) R/W 32 bits undefined 11.3.2/11-15
0x10118 Base register bank 3 (BR3) R/W 32 bits 0x0000_0000 11.3.1/11-13
0x1011C Option register bank 3 (OR3) R/W 32 bits undefined 11.3.2/11-15
0x10120 Base register bank 4 (BR4) R/W 32 bits 0x0000_0000 11.3.1/11-13
0x10124 Option register bank 4 (OR4) R/W 32 bits undefined 11.3.2/11-15
0x10128 Base register bank 5 (BR5) R/W 32 bits 0x0000_0000 11.3.1/11-13
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register R/W Size Reset Section/Page