Freescale Semiconductor MPC8260 - Manual (Page 40)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
xxxviii Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
33.4.6.2 Delay Compensation Buffers (DCB)................................................................... 33-49
33.4.7 IMA Exceptions ....................................................................................................... 33-49
33.4.7.1 IMA Interrupt Queue Entry ................................................................................. 33-50
33.4.7.2 ICP Cell Reception Exceptions ........................................................................... 33-51
33.4.8 IDCR Timer Programming ...................................................................................... 33-52
33.4.8.1 IDCR Master Clock ............................................................................................. 33-52
33.4.8.2 IDCR FCC Parameter Shadow ............................................................................ 33-52
33.4.8.2.1 PowerQUICC II Features Unavailable if IDCR is Used ................................. 33-52
33.4.8.2.2 Programming the FCC Parameter Shadow...................................................... 33-53
33.4.8.2.3 On-the-Fly Changes of FCC Parameters ......................................................... 33-53
33.4.8.3 IDCR_Init Command........................................................................................... 33-54
33.4.8.4 IDCR Root Parameters ........................................................................................ 33-54
33.4.8.5 IDCR Table Entry ................................................................................................ 33-54
33.4.8.6 IDCR Counter Algorithm .................................................................................... 33-55
33.4.8.7 IDCR Events ........................................................................................................ 33-55
33.4.9 APC Programming for IMA .................................................................................... 33-56
33.4.9.1 Programming for CBR, UBR, VBR, and UBR+ ................................................. 33-57
33.4.9.2 Programming for ABR ........................................................................................ 33-57
33.4.10 Changing IMA Version............................................................................................ 33-58
33.5 IMA Software Interface and Requirements ................................................................. 33-58
33.5.1 Software Model........................................................................................................ 33-58
33.5.2 Initialization Procedure............................................................................................ 33-59
33.5.3 Software Responsibilities ........................................................................................ 33-59
33.5.3.1 System Definition ................................................................................................ 33-59
33.5.3.2 General Operation................................................................................................ 33-60
33.5.3.3 Receive Link State Machine Control................................................................... 33-60
33.5.3.4 Receive Group State Machine Control ................................................................ 33-60
33.5.3.5 Transmit Link State Machine Control ................................................................. 33-60
33.5.3.6 Transmit Group State Machine Control............................................................... 33-61
33.5.3.7 Group Symmetry Control .................................................................................... 33-61
33.5.3.8 ICP End-to-End Channel Transmission............................................................... 33-61
33.5.3.9 Link Addition and Slow Recovery (LASR) Procedure ....................................... 33-61
33.5.3.10 Failure Alarms ..................................................................................................... 33-61
33.5.3.11 Test Pattern Control ............................................................................................. 33-62
33.5.3.12 Performance Parameter Measurement and Reporting ......................................... 33-62
33.5.3.13 SNMP MIBs ........................................................................................................ 33-62
33.5.4 IMA Software Procedures ....................................................................................... 33-62
33.5.4.1 Transmit ICP Cell Signalling............................................................................... 33-62
33.5.4.2 Receive Link Start-up Procedure ......................................................................... 33-62
33.5.4.3 Group Start-up Procedure ................................................................................... 33-63
33.5.4.3.1 As Initiator (TX).............................................................................................. 33-64