Freescale Semiconductor MPC8260 - Manual (Page 165)

Memory Map
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 3-19
0x11A37 SCC2 status register (SCCS2) R/W 8 bits 0x00 21.20/21-21
(UART)
22.12/22-14
(HDLC)
23.15/23-16
(BISYNC)
24.13/24-12
(Transparent)
0x11A38–
0x11A3F
Reserved — 8 bytes — —
SCC3
0x11A40 SCC3 general mode register (GSMR_L3) R/W 32 bits 0x0000_0000 20.1.1/20-3
0x11A44 SCC3 general mode register (GSMR_H3) R/W 32 bits 0x0000_0000
0x11A48 SCC3 protocol-specific mode register (PSMR3) R/W 16 bits 0x0000 20.1.2/20-9
21.16/21-12
(UART)
22.8/22-7
(HDLC)
23.11/23-10
(BISYNC)
24.9/24-8
(Transparent)
25.17/25-14
(Ethernet)
0x11A4A Reserved — 16 bits — —
0x11A4C SCC3 transmit on demand register (TODR3) R/W 16 bits 0x0000 20.1.4/20-10
0x11A4E SCC3 data synchronization register (DSR3) R/W 16 bits 0x7E7E 20.1.3/20-9
0x11A50 SCC3 event register (SCCE3) R/W 16 bits 0x0000 21.19/21-19
(UART)
22.11/22-12
(HDLC)
23.14/23-15
(BISYNC)
24.12/24-11
(Transparent)
25.20/25-20
(Ethernet)
0x11A54 SCC3 mask register (SCCM3) R/W 16 bits 0x0000
0x11A56 Reserved — 8 bits — —
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register R/W Size Reset Section/Page