Freescale Semiconductor MPC8260 - Manual (Page 44)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
xlii Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
38.3.1 The SPI as a Master Device ....................................................................................... 38-3
38.3.2 The SPI as a Slave Device ......................................................................................... 38-4
38.3.3 The SPI in Multimaster Operation............................................................................. 38-4
38.4 Programming the SPI Registers ..................................................................................... 38-6
38.4.1 SPI Mode Register (SPMODE) ................................................................................. 38-6
38.4.1.1 SPI Examples with Different SPMODE[LEN] Values.......................................... 38-8
38.4.2 SPI Event/Mask Registers (SPIE/SPIM) ................................................................... 38-9
38.4.3 SPI Command Register (SPCOM) .......................................................................... 38-10
38.5 SPI Parameter RAM .................................................................................................... 38-10
38.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR).................................... 38-12
38.6 SPI Commands ............................................................................................................ 38-12
38.7 The SPI Buffer Descriptor (BD) Table ........................................................................ 38-13
38.7.1 SPI Buffer Descriptors (BDs) .................................................................................. 38-13
38.7.1.1 SPI Receive BD (RxBD) ..................................................................................... 38-14
38.7.1.2 SPI Transmit BD (TxBD) .................................................................................... 38-15
38.8 SPI Master Programming Example ............................................................................. 38-16
38.9 SPI Slave Programming Example................................................................................ 38-17
38.10 Handling Interrupts in the SPI ..................................................................................... 38-18
Chapter 39
I
2
C Controller
39.1 Features .......................................................................................................................... 39-2
39.2 I
2
C Controller Clocking and Signal Functions .............................................................. 39-2
39.3 I
2
C Controller Transfers ................................................................................................ 39-2
39.3.1 I
2
C Master Write (Slave Read).................................................................................. 39-3
39.3.2 I
2
C Loopback Testing ................................................................................................ 39-4
39.3.3 I
2
C Master Read (Slave Write).................................................................................. 39-4
39.3.4 I
2
C Multi-Master Considerations .............................................................................. 39-5
39.4 I
2
C Registers .................................................................................................................. 39-6
39.4.1 I
2
C Mode Register (I2MOD)..................................................................................... 39-6
39.4.2 I
2
C Address Register (I2ADD).................................................................................. 39-6
39.4.3 I
2
C Baud Rate Generator Register (I2BRG) ............................................................. 39-7
39.4.4 I
2
C Event/Mask Registers (I2CER/I2CMR) ............................................................. 39-7
39.4.5 I
2
C Command Register (I2COM).............................................................................. 39-8
39.5 I
2
C Parameter RAM....................................................................................................... 39-9
39.6 I
2
C Commands............................................................................................................. 39-11
39.7 The I
2
C Buffer Descriptor (BD) Table ........................................................................ 39-11
39.7.1 I
2
C Buffer Descriptors (BDs) .................................................................................. 39-12
39.7.1.1 I
2
C Receive Buffer Descriptor (RxBD)............................................................... 39-12
39.7.1.2 I
2
C Transmit Buffer Descriptor (TxBD) ............................................................. 39-13