Freescale Semiconductor MPC8260 - Manual (Page 38)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
xxxvi Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
32.4.1 Receiver Overview .................................................................................................. 32-20
32.4.2 Mapping of PHY | VP | VC | CID............................................................................ 32-21
32.4.3 AAL2 Switching ...................................................................................................... 32-22
32.4.4 AAL2 RX Data Structures ....................................................................................... 32-23
32.4.4.1 AAL2 Protocol-Specific RCT ............................................................................. 32-24
32.4.4.2 CID Mapping Tables and RxQDs........................................................................ 32-27
32.4.4.3 CPS Rx Queue Descriptors.................................................................................. 32-27
32.4.4.4 CPS Receive Buffer Descriptor (RxBD) ............................................................. 32-28
32.4.4.5 CPS Switch Rx Queue Descriptor ....................................................................... 32-29
32.4.4.6 SWITCH Receive/Transmit Buffer Descriptor (RxBD)...................................... 32-30
32.4.4.7 SSSAR Rx Queue Descriptor .............................................................................. 32-31
32.4.4.8 SSSAR Receive Buffer Descriptor ...................................................................... 32-33
32.5 AAL2 Parameter RAM ................................................................................................ 32-35
32.6 User-Defined Cells in AAL2 ....................................................................................... 32-38
32.7 AAL2 Exceptions ........................................................................................................ 32-38
Chapter 33
Inverse Multiplexing for ATM (IMA)
33.1 Features .......................................................................................................................... 33-1
33.1.1 References.................................................................................................................. 33-3
33.1.2 IMA Versions Supported ........................................................................................... 33-3
33.1.3 PowerQUICC II Versions Supported ......................................................................... 33-3
33.1.4 PHY-Layer Devices Supported.................................................................................. 33-3
33.1.5 ATM Features Not Supported .................................................................................... 33-4
33.1.6 Additional Impact on PowerQUICC II Features ....................................................... 33-4
33.2 IMA Protocol Overview ............................................................................................... 33-4
33.2.1 Introduction................................................................................................................ 33-4
33.2.2 IMA Frame Overview................................................................................................ 33-5
33.2.3 Overview of IMA Cells ............................................................................................. 33-7
33.2.3.1 IMA Control Cells ................................................................................................. 33-7
33.2.3.2 IMA Filler Cells................................................................................................... 33-10
33.3 IMA Microcode Architecture ...................................................................................... 33-10
33.3.1 IMA Function Partitioning....................................................................................... 33-10
33.3.1.1 User Plane Functions Performed by Microcode .................................................. 33-11
33.3.1.2 Plane Management Functions Performed by Microcode..................................... 33-11
33.3.2 Transmit Architecture .............................................................................................. 33-11
33.3.2.1 TRL Operation..................................................................................................... 33-12
33.3.2.1.1 TRL Service Latency....................................................................................... 33-13
33.3.2.2 Non-TRL Operation............................................................................................. 33-13
33.3.2.3 Transmit Queue Operation Examples (ITC mode).............................................. 33-14