Freescale Semiconductor MPC8260 - Manual (Page 1189)

ATM Transmission Convergence Layer
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 34-11
34.4.1.4 TC Layer Mask Register (TCMRx)
This register’s field description is identical to that of TCER (refer to Section 34.4.1.3, “TC Layer Event
Register [1–8] (TCERx)” ). Each bit that is set in TCMR enables an interrupt when the corresponding bit
in TCER is set.
34.4.2 TC Layer General Registers
The TC layer general registers are registers that are distributed to all of the TC blocks. Each TC block is
represented by specific bits. When accessing a general register each TC block is responsible for its specific
bits only.
34.4.2.1 TC Layer General Event Register (TCGER)
The TC layer general event register (TCGER), as shown in Figure 34-8 , summarizes the events for all the
TC blocks. Each bit stands for an ORed event register of a TC block. Once a bit is set, it indicates that one
or more event bits are set in the corresponding TC block event register.
Table 34-5 describes TCGER fields.
34.4.2.2 TC Layer General Status Register (TCGSR)
Figure 34-9 shows the TC layer general status register (TCGSR), which records the cell delineation and
transmit FIFO status for all TC blocks.
0 1 2 3 4 5 6 7 8 15
Field TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 —
Reset 0000_0000_0000_0000
R/W R/W
Figure 34-8. TC Layer General Event Register (TCGER)
Table 34-5. TCGER Field Descriptions
Bits Name Description
0 TC1 One bit or more is set in TC1 event register.
1 TC2 One bit or more is set in TC2 event register.
2 TC3 One bit or more is set in TC3 event register.
3 TC4 One bit or more is set in TC4 event register.
4 TC5 One bit or more is set in TC5 event register.
5 TC6 One bit or more is set in TC6 event register.
6 TC7 One bit or more is set in TC7 event register.
7 TC8 One bit or more is set in TC8 event register.