Freescale Semiconductor MPC8260 - Manual (Page 479)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-61
Figure 11-53. GPCM Read Followed by Write (OR x[29–30] = 10)
11.5.2 External Access Termination
External access termination is supported by the GPCM using GTA, which is synchronized and sampled
internally by the PowerQUICC II. If, during a GPCM data phase (second cycle or later), the sampled signal
is asserted, it is converted to PSDVAL, which terminates the current GPCM access. GTA should be
asserted for one cycle. Note that because GTA is synchronized, bus termination may occur three cycles
after GTA assertion, so in case of read cycle, the device still must output data as long as OE is asserted.
The user selects whether PSDVAL is generated internally or externally (by means of GTA assertion) by
resetting/setting ORx[SETA].
Figure 11-54 shows how a GPCM access is terminated by GTA assertion. Asserting GTA terminates an
access even if ORx[SETA] = 0 (internal PSDVAL generation).
Clock
Address
PSDVAL
CSx
CSy
BCTL x
OE
Data
Hold Time