Freescale Semiconductor MPC8260 - Manual (Page 1341)

Index J–M
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor Index-13
IDCR mode group activation, 33-74
start-up, 33-73
link addition, 33-65
Rx steps, 33-65
TX parameters, 33-66
link receive deactivation procedure, 33-68
link receive reactivation, 33-69
link removal, 33-67
Rx steps, 33-67
TX parameters, 33-68
receive event response, 33-70
receive link start-up procedure, 33-62
test pattern, 33-72
as initiator (NE), 33-72
as responder (FE), 33-72
transmit event response, 33-70
transmit ICP cell signalling, 33-62
TRL on-the-fly change, 33-69
software responsibilities, 33-59
failure alarms, 33-61
general operation, 33-60
group symmetry control, 33-61
ICP end-to-end channel transmission, 33-61
link addition and slow recovery (LASR), 33-61
performance parameter measurement and reporting,
33-62
receive group state machine control, 33-60
receive link state machine control, 33-60
SNMP MIBs, 33-62
system definition, 33-59
test pattern control, 33-62
transmit group state machine control, 33-61
transmit link state machine control, 33-60
IMMR (internal memory map register), 4-36
Input/output port memory map, 3-7
Instruction field conventions, 1-lxxxvii
Instruction timing overview, 2-27
Instruction unit, 2-5
Integer unit overview, 2-6
Interrupts
ATM interrupt queues, 30-81
RISC timer tables
interrupt handling, 14-26
SCC interrupt handling, 20-16
Inverse Multiplexing for ATM (IMA)
see IMA, 33-1
J
JTAG implementation, 13-5
L
L_TESCR1 (local bus transfer error status and control
register 1), 4-42
L_TESCR2 (local bus transfer error status and control
register 2), 4-43
L_TESCRx (local bus error status and control registers),
11-33
LCL_ACR (local bus arbiter configuration register), 4-31
LCL_ALRH (local bus arbitration high-level register), 4-32
LCL_ALRL (local bus arbitration low-level register), 4-32
LDTEA (SDMA local bus transfer error address register),
19-4
LDTEM (SDMA local bus transfer error MSNUM register),
19-4
Loopback mode, 15-7
LSDMR (local bus SDRAM mode register), 11-23
LSRT (local bus-assigned SDRAM refresh timer) register,
11-31
LURT (local bus-assigned UPM refresh timer) register, 11-30
M
MCCE (MCC event) register, 28-37
MCCFx (MCC configuration registers), 28-33
MCCM (MCC mask) register, 28-37
MDR (memory data register), 11-28
Memory controller
address checking, 11-7
address latch enable (ALE), 11-10
address space checking, 11-7
architecture overview, 11-4
atomic bus operation, 11-9
basic architecture, 11-4
basic operation, 11-7
boot chip-select operation, 11-62
controlling the timing of GPL1, GPL2, and CSx, 11-69
CSx timing example, 11-69
delayed read, 11-9
EDO interface connection, MPC8260 to 60x bus, 11-92
error checking and correction (ECC), 11-8
external master support, 11-101
external support, 11-10
features common to all machines, 11-5
features list, 11-3
general-purpose chip-select machine (GPCM)
access termination, external, 11-61
assertion timing, 11-53
common features, 11-5
differences between MPC8xx and MPC8260, 11-63
external access termination, 11-61
implementation differences with UPMs and SDRAM
machine, 11-6