Freescale Semiconductor MPC8260 - Manual (Page 1098)

ATM AAL2
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
32-36 Freescale Semiconductor
0x62 APCP_BASE Hword APC parameters table base address. User-defined.
0x64 FBT_BASE Hword Free buffer pool parameters table base. User-defined.
0x66 INTT_BASE Hword Interrupt queue parameters table base. User-defined.
0x68 — — Reserved. Should be cleared during initialization.
0x6A UNI_STATT_BASE Hword UNI statistics table base. User-defined.
0x6C BD_BASE_EXT Word BD table base address extension. BD_BASE_EXT[0-7] hold the 8 most
significant bits of the RX/TxBD table base address.
BD_BASE_EXT[8-31] should be zero. User-defined.
0x70 VPT_BASE /
EXT_CAM_BASE Word Base address of the address compression VP table/external CAM.
User-defined.
0x74 VCT_BASE Word Base address of the address compression VC table. User-defined.
0x78 VPT1_BASE /
EXT_CAM1_BASE Word Base address of the address compression VP1 table/EXT CAM1.
User-defined.
0x7C VCT1_BASE Word Base address of the address compression VC1 table. User-defined.
0x80 VP_MASK Hword VP mask for address compression lookup. User-defined.
0x82 VCI_Filtering Hword VCI filtering enable bits. When cells with VCI = 3, 4, 6, 7-15 are received
and the associated VCI_Filtering bit = 1 the cell is sent to the raw cell
queue. VCI=3 is associated with VCI_Filtering[3], VCI=15 is associated
with VCI_Filtering[15]. VCI_Filtering[0–2, 5] should be zero. See
Section 30.10.1.2, “VCI Filtering (VCIF) .”
0x84 GMODE Hword Global mode. User-defined. See Section 30.10.1.3, “Global Mode Entry
(GMODE) .”
0x86 COMM_INFO Hword The information field associated with the last host command.
User-defined. See
Section 30.14, “ATM Transmit Command . “
0x88 Hword
0x8A Hword
0x8C — Word Reserved. Should be cleared during initialization.
0x90 CRC32_PRES Word Preset for CRC32. Initialize to 0xFFFFFFFF.
0x94 CRC32_MASK Word Constant mask for CRC32. Initialize to 0xDEBB20E3.
0x98 AAL1_SNPT_BASE Hword AAL1 SN protection look up table base address. (AAL1 only.) The
32-byte table resides in dual-port RAM and must be initialized by the user
(See
Section 30.10.6, “AAL1 Sequence Number (SN) Protection Table ”).
0x9A — Hword Reserved. Should be cleared during initialization.
0x9C SRTS_BASE Word External SRTS logic base address. (AAL1 only.) Should be 16-byte
aligned.
0xA0 IDLE/UNASSIGN_BASE Hword Idle/unassign cell base address. Points to dual-port RAM area contains
idle/unassign cell template (little-endian format). Should be 64-byte
aligned. User-defined. The ATM header should be 0x0000_0000 or
0x0100_0000 (CLP=1).
0xA2 IDLE/UNASSIGN_SIZE Hword Idle/Unassign cell size. 52 in regular mode. 53–64 in UDC mode.
Table 32-13. AAL2 Parameter RAM (continued)
Offset Name Width Description