Freescale Semiconductor MPC8260 - Manual (Page 453)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-35
11.4.1 Supported SDRAM Configurations
The PowerQUICC II memory controller supports any SDRAM configuration under the restrictions that all
SDRAM devices that reside on the same bus (60x or local) should have the same port size and timing
parameters. For more information, refer to Application Note 2165, “MPC8260 SDRAM Support” (order
number AN2165/D).
11.4.2 SDRAM Power-On Initialization
At system reset, initialization software must set up the programmable parameters in the memory controller
banks registers (ORx, BRx, P/LSDMR). After all memory parameters are configured, system software
should execute the following initialization sequence for each SDRAM device.
1. Issue a PRECHARGE - ALL - BANKS command
2. Issue eight CBR REFRESH commands
NOTE
If the SDRAM does not require eight CBR REFRESH COMMANDS , then the
SDRAM requirement should be followed.
3. Issue a MODE - SET command to initialize the mode register
The initial commands are executed by setting P/LSDMR[OP] and accessing the SDRAM with a
single-byte transaction. See Figure 11-10 on page 11-20.
Note that software should ensure that no memory operations begin until this process completes.
11.4.3 JEDEC-Standard SDRAM Interface Commands
The PowerQUICC II performs all accesses to SDRAM by using JEDEC-standard SDRAM interface
commands. The SDRAM device samples the command and data inputs on the rising edge of the
PowerQUICC II bus clock. Data at the output of the SDRAM device must be sampled on the rising edge
of the PowerQUICC II bus clock.
As seen in Table 11-19 , the PowerQUICC II provides the following SDRAM interface commands: