Freescale Semiconductor MPC8260 - Manual (Page 462)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-44 Freescale Semiconductor
Figure 11-29. SDRAM Single-Beat Read, Page Hit, CL = 3
Figure 11-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 3
Figure 11-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11] Column
WE
DQM
Data D0
Z
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11] Row Column
WE
DQM
Data D0 D1
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11]
WE
DQM
Data D0
Z A10 = 1
BS *
* BS—Bank select according to SDRAM organization. A10 = 1 means all banks are precharged.
Row
CAS Latency = 3
Col
D1 D2 D4
Deactivate Activate