Freescale Semiconductor MPC8260 User Manual
Page 83
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor
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describes the PowerQUICC II implementation of HDLC
protocol.
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Chapter 23, “SCC BISYNC Mode,”
describes the PowerQUICC II implementation of
byte-oriented BISYNC protocol developed by IBM for use in networking products.
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Chapter 24, “SCC Transparent Mode,”
describes the PowerQUICC II implementation of
transparent mode (also called totally transparent mode), which provides a clear channel on
which the SCC can send or receive serial data without bit-level manipulation.
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Chapter 25, “SCC Ethernet Mode,”
describes the PowerQUICC II implementation of Ethernet
protocol.
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Chapter 26, “SCC AppleTalk Mode,”
describes the PowerQUICC II implementation of
AppleTalk.
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Chapter 27, “Serial Management Controllers (SMCs),”
describes two serial management
controllers, full-duplex ports that can be configured independently to support one of three
protocols—UART, transparent, or general-circuit interface (GCI).
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Chapter 28, “Multi-Channel Controllers (MCCs),”
describes the PowerQUICC II’s
multi-channel controller (MCC), which handles up to 128 serial, full-duplex data channels.
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Chapter 29, “Fast Communications Controllers (FCCs),”
describes the PowerQUICC II’s fast
communications controllers (FCCs), which are SCCs optimized for synchronous high-rate
protocols.
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Chapter 30, “ATM Controller and AAL0, AAL1, and AAL5,”
describes the PowerQUICC II
ATM controller, which provides the ATM and AAL layers of the ATM protocol. The ATM
controller performs segmentation and reassembly (SAR) functions of AAL5, AAL1, and
AAL0, and most of the common parts convergence sublayer (CP-CS) of these protocols.
Chapter 31, “ATM AAL1 Circuit Emulation Service,”
describes the implementation of circuit
emulation service (CES) using ATM adaptation layer type 1 (AAL1) on the PowerQUICC II.
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describes he functionality and data structures of ATM adaptation
layer type 2 (AAL2) CPS, CPS switching, and SSSAR.
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Chapter 33, “Inverse Multiplexing for ATM (IMA),”
describes specifications for the inverse
multiplexing for ATM (IMA) microcode.
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Chapter 34, “ATM Transmission Convergence Layer,”
describes how the PowerQUICC II can
support applications which receive ATM traffic over the standard serial protocols like E1, T1,
and xDSL via its serial interface (SIx TDMx and NMSI) ports because of its internally
implemented TC-layer functionality.
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Chapter 35, “Fast Ethernet Controller,”
describes the PowerQUICC II’s implementation of the
Ethernet IEEE 802.3 protocol.
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Chapter 36, “FCC HDLC Controller,”
describes the FCC implementation of the HDLC
protocol.
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Chapter 37, “FCC Transparent Controller,”
describes the FCC implementation of the
transparent protocol.
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Chapter 38, “Serial Peripheral Interface (SPI),”
describes the serial peripheral interface, which
allows the PowerQUICC II to exchange data between other PowerQUICC II chips, the