Freescale Semiconductor MPC8260 - Manual (Page 95)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 1-1
Chapter 1
Overview
The PowerQUICC II™ is a versatile communications processor that integrates on one chip a
high-performance PowerPC™ RISC microprocessor, a very flexible system integration unit, and many
communications peripheral controllers that can be used in a variety of applications, particularly in
communications and networking systems.
The G2 core is an embedded variant of the MPC603e™ microprocessor with 16 Kbytes of instruction
cache and 16 Kbytes of data cache. The system interface unit (SIU) consists of a flexible memory
controller that interfaces to almost any user-defined memory system, a 60x-to-PCI bus bridge (MPC8250,
MPC8265, and MPC8266 only), and many other peripherals making this device a complete system on a
chip.
The communications processor module (CPM) includes all the peripherals found in the PowerQUICC
(MPC860), with the addition of three high-performance communication channels that support new
emerging protocols (for example, 155-Mbps ATM and Fast Ethernet). The PowerQUICC II has dedicated
hardware that can handle up to 256 full-duplex, time-division-multiplexed logical channels.
This document describes the functional operation of PowerQUICC II, with an emphasis on peripheral
functions.
Chapter 2, “G2 Core,” is an overview of the microprocessor core; detailed information about
the core can be found in the G2 Core Reference Manual (order number: G2CORERM/D).
1.1 Features
The following is an overview of the PowerQUICC II feature set:
• Dual-issue integer core
— A core version of the MPC603e microprocessor
— System core microprocessor supporting the following frequencies:
– 133–200 MHz (.29
µm (HiP3) devices)
– 150–300 MHz (.25
µm (HiP4) devices)
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— Supports bus snooping for cache coherency