Freescale Semiconductor MPC8260 - Manual (Page 860)

Multi-Channel Controllers (MCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
28-12 Freescale Semiconductor
28.3.2.1 Internal Transmitter State (TSTATE)—Transparent Mode
In transparent mode, TSTATE functions the same as in HDLC mode. For a description, refer to Section
28.3.1.1.
28.3.2.2 Interrupt Mask (INTMSK)—Transparent Mode
In transparent mode, INTMSK functions the same as in HDLC mode. For a description, refer to Section
28.3.2.2.
0x24 ZDSTATE Word Zero-deletion machine state. Initialize ZDSTATE as in the following table:
0x28 ZDDATA0 Word Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)
0x2C ZDDATA1 Word Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)
0x30 RBDFlags Hword RxBD flags, used by the CP (read-only for the user)
0x32 RBDCNT Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only
for the user)
0x34 RBDPTR Word Rx internal data pointer. Points to current absolute data address of channel, used by the
CP (read-only for the user)
0x38 TMRBLR Hword Transparent maximum receive buffer length. Defines the maximum number of bytes
written to a receiver buffer before moving to the next buffer for the respective channel.
This value must be 8 byte aligned.
0x3A RCVSYNC Hword Receive synchronization pattern. Defines the synchronization pattern when
CHAMR[SYNC] is 0b1x. The two bytes are checked in reverse order (byte from address
0x3B first and byte from address 0x3A last). Non-inverted data is used for
synchronization even if the channel is programmed to invert the data. Clear RCVSYNC
when CHAMR[SYNC] = 0b0x.
0x3C — Word Reserved
1 The offset is relative to dual-port RAM address 64*CH_NUM
Table 28-6. Channel-Specific Parameters for Transparent Operation (continued)
Offset
1
Name Width Description
Channel Type RCVSYNC
ZDSTATE Initial
Programmed Value
If pattern synchronization is used (CHAMR[SYNC] = 1x), then…
Regular 0bxxxx_xxxx_xxxx_xxx0 0x00FF_FFE0
0bxxxx_xxxx_xxxx_xxx1 0x0000_0000
Inverted 0bxxxx_xxxx_xxxx_xxx0 0x20FF_FFE0
0bxxxx_xxxx_xxxx_xxx1 0x2000_0000
If pattern synchronization is not used (CHAMR[SYNC] = 00), then…
Regular 0x0000 0x50FF_FFE0
Inverted 0x0000 0x70FF_FFE0