Freescale Semiconductor MPC8260 - Manual (Page 1336)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Index-8 Freescale Semiconductor
D–D Index
master mode, 38-3
maximum receive buffer length (MRBLR), 38-11
multi-master operation, 38-4
parameter RAM, 38-10
programming example
master, 38-16
slave, 38-17
programming model, 38-6
RxBD, 38-14
slave mode, 38-4
SPCOM, 38-10
SPIE, 38-9
SPIM, 38-9
SPMODE, 38-6
TxBD, 38-15
system interface unit (SIU)
60x bus monitor function, 4-2
add flexibility to CPM interrupt priorities, 4-12
BCR, 4-26
block diagram, 4-1
bus monitor, 4-3
clocks, 4-3
configuration functions, 4-2
configuration/protection logic block diagram, 4-3
encoding the interrupt vector, 4-14
FCC relative priority, 4-12
flexibility of interrupt priorities, 4-12
highest priority interrupt, 4-13
IMMR, 4-36
interrupt controller features list, 4-7
interrupt priorities, add flexibility, 4-12
interrupt source priorities, 4-9
interrupt vector calculation, 4-14
interrupt vector encoding, 4-14
interrupt vector generation, 4-14
L_TESCR1, 4-42
L_TESCR2, 4-43
LCL_ACR, 4-31
LCL_ALRH, 4-32
LCL_ALRL, 4-32
local bus monitor function, 4-2
masking interrupt sources, 4-13
MCC relative priority, 4-12
periodic interrupt timer (PIT), 4-5
periodic interrupt timer (PIT) function, 4-2
pin multiplexing, 4-49
PISCR, 4-46
PITC, 4-46
PITR, 4-47
port C interrupts, 4-16
PPC_ACR, 4-29
PPC_ALRH, 4-30
PPC_ALRL, 4-31
programming model, 4-17
registers, 4-17
SCC relative priority, 4-12
SCPRR_H, 4-19
SCPRR_L, 4-20
SICR, 4-17
SIEXR, 4-25
signal multiplexing, 4-49
SIMR_H, 4-22
SIMR_L, 4-23
SIPNR_H, 4-21
SIPNR_L, 4-21
SIPRR, 4-18
SIUMCR, 4-33
SIVEC, 4-24
software watchdog timer, 4-6
SWR, 4-7
SWSR, 4-38
SYPCR, 4-37
system protection, 4-2
TESCR1, 4-38
TESCR2, 4-40
time counter (TMCNT)
function, 4-2
overview, 4-4
timers, 4-3
TMCNT, 4-44
TMCNTAL, 4-45
TMCNTSC, 4-44
timers
memory map, 3-8
Conventions
notational conventions, 1-lxxxiii, II-1, III-2, IV-3
terminology, 1-lxxxvi
CPCR (CP command register), 14-13
CPM multiplexing logic (CMX)
overview, 16-1
see also Serial interface (SI)
CPM multiplexing, see CPM multiplexing logic (CMX)
CPM MUX memory map, 3-21
CPM MUX, see CPM multiplexing logic (CMX)
CxTx (chip-select signals), 11-74
D
DCM (IDMA channel mode), 19-19
Digital phase-locked loop (DPLL) operation, 20-21
DSR (data synchronization register)
overview, 20-9
UART mode, 21-10
Dual-port RAM
accessing dual-port RAM, 14-18