Freescale Semiconductor MPC8260 - Manual (Page 924)

ATM Controller and AAL0, AAL1, and AAL5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
30-4 Freescale Semiconductor
— Performs ATMF UNI 4.0 ABR flow control on a per-VC basis
— Automatic forward-RM, backward-RM cells generation
— Automatic feedback rate adaptation
— Support for EFCI (explicit forward congestion indication) and ER (explicit rate)
— RM cell floating-point calculations
— Fully managed by CP with no host intervention
• Receive address look-up mechanism
— Two modes of address look-up are supported
– External CAM
– Address compression
• OAM (operations and maintenance) cells
— OAM filtering according to PTI field and reserved VCI field
— Raw cell queues for transmission and reception
— CRC-10 generation/check
— Performance monitoring support
– Support up to 64 bidirectional block tests simultaneously
– Automatic FMC and BRC cell generation and termination
– User transmit cell
0+1
count
– User transmit cell
0
count
– PM cells time stamp insertion
– Block error detection code (BEDC
0+1
) generation/check
– Total receive cell
0+1
count
– Total receive cell
0
count
— Specifying channel code for F5 OAM cells
• ATM layer statistic gathering on a per PHY basis.
— UTOPIA receiver error cells count (Rx parity error or short/long cells error)
— Misinserted cell count
— CRC-10 error cells count (ABR flow only)
• Memory management
— RxBD table per VC with option of global free buffer pool for AAL5
— TxBD table per VC
30.2 ATM Controller Overview
The following sections provide an overview of the transmitter and receiver portions of the ATM controller.