Freescale Semiconductor MPC8260 - Manual (Page 553)

Communications Processor Module Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 14-5
• 64-bit dual-port RAM access
• Optimized for communications processing
• Performs DMA bursting of serial data from/to dual-port RAM to/from external memory. Note that
IDMA cannot burst to dual-port RAM.
14.3.3 CP Block Diagram
The CP contains the following functional units:
• Scheduler and sequencer
• Instruction decoder
• Execution unit
• Load/store unit (LSU)
• Block transfer module (BTM)—moves data between serial FIFO and RAM
• Eight general purpose registers (GPRs)
• Special registers, CRC machine, HDLC framer
The CP also gives SDMA commands to the SDMA. The CP interfaces with the dual-port RAM for loading
and storing data and for fetching instructions while running microcode from dual-port RAM.
Figure 14-2 shows the CP block diagram.