Freescale Semiconductor MPC8260 - Manual (Page 750)

SCC HDLC Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
22-22 Freescale Semiconductor
22.15.6 HDLC Bus Protocol Programming
The HDLC bus on the PowerQUICC II is implemented using the SCC in HDLC mode with bus-specific
options selected in the PSMR and GSMR, as outlined below. See also
Section 22.5, “Programming the
SCC in HDLC Mode.”
22.15.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol
To program the protocol-specific mode register (PSMR), set the bits as described below:
• Configure NOF as preferred
• Set RTE and BUS to 1
• Set BRM to 1 if delayed RTS is desired
• Configure CRC to 16-bit CRC CCITT (0b00).
• Configure other bits to zero or default.
To program the general SCC mode register (GSMR), set the bits as described below:
• Set MODE to HDLC mode (0b0000).
• Configure CTSS to 1 and all other bits to zero or default.
• Configure the DIAG bits for normal operation (0b00).
• Configure RDCR and TDCR for 1
× clock (0b00).
• Configure TENC and RENC for NRZ (0b000).
• Clear RTSM to send idles between frames.
• Set GSMR_L[ENT, ENR] as the last step to begin operation.
22.15.6.2 HDLC Bus Controller Programming Example
Except for the above discussion in Section 22.15.6.1, “Programming GSMR and PSMR for the HDLC Bus
Protocol,” use the example in Section 22.14, “SCC HDLC Programming Example #1.”