Freescale Semiconductor MPC8260 - Manual (Page 151)

Memory Map
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 3-5
0x10458 Outbound message register 0 (OMR0) 2 R/W 32 bits undefined 9.12.1.2/9-66
0x1045C Outbound message register 1 (OMR1) 2 R/W 32 bits undefined 9.12.1.2/9-66
0x10460 Outbound doorbell register (ODR) 2 R/W 32 bits 0x0000_0000 9.12.2.1/9-67
0x10468 Inbound doorbell register (IDR) 2 R/W 32 bits 0x0000_0000 9.12.2.2/9-68
0x10480 Inbound message interrupt status register (IMISR)
2
R/W 32 bits 0x0000_0000 9.12.3.4.5/9-80
0x10484 Inbound message interrupt mask register (IMIMR)
2
R/W 32 bits 0x0000_0000 9.12.3.4.6/9-82
0x104A0 Inbound free_FIFO head pointer register (IFHPR)
2
R/W 32 bits 0x0000_0000 9.12.3.2.1/9-71
0x104A8 Inbound free_FIFO tail pointer register (IFTPR)
2
R/W 32 bits 0x0000_0000 9.12.3.2.1/9-71
0x104B0 Inbound post_FIFO head pointer register (IPHPR)
2
R/W 32 bits 0x0000_0000 9.12.3.2.2/9-72
0x104B8 Inbound post_FIFO tail pointer register (IPTPR)
2
R/W 32 bits 0x0000_0000 9.12.3.2.2/9-72
0x104C0 Outbound free_FIFO head pointer register (OFHPR)
2
R/W 32 bits 0x0000_0000 9.12.3.3.1/9-74
0x104C8 Outbound free_FIFO tail pointer register (OFTPR)
2
R/W 32 bits 0x0000_0000 9.12.3.3.1/9-74
0x104D0 Outbound post_FIFO head pointer register (OPHPR)
2
R/W 32 bits 0x0000_0000 9.12.3.3.2/9-75
0x104D8 Outbound post_FIFO tail pointer register (OPTPR)
2
R/W 32 bits 0x0000_0000 9.12.3.3.2/9-75
0x104E4 Message unit control register (MUCR)
2
R/W 32 bits 0x0000_0002 9.12.3.4.7/9-83
0x104F0 Queue base address register (QBAR)
2
R/W 32 bits 0x0000_0000 9.12.3.4.8/9-84
0x10500 DMA 0 mode register (DMAMR0)
2
R/W 32 bits 0x0000_0000 9.13.1.6.1/9-88
0x10504 DMA 0 status register (DMASR0)
2
R/W 32 bits 0x0000_0000 9.13.1.6.2/9-90
0x10508 DMA 0 current descriptor address register (DMACDAR0)
2
R/W 32 bits 0x0000_0000 9.13.1.6.3/9-91
0x10510 DMA 0 source address register (DMASAR0)
2
R/W 32 bits 0x0000_0000 9.13.1.6.4/9-92
0x10518 DMA 0 destination address register (DMADAR0)
2
R/W 32 bits 0x0000_0000 9.13.1.6.5/9-92
0x10520 DMA 0 byte count register (DMABCR0)
2
R/W 32 bits 0x0000_0000 9.13.1.6.6/9-93
0x10524 DMA 0 next descriptor address register (DMANDAR0)
2
R/W 32 bits 0x0000_0000 9.13.1.6.7/9-94
0x10580 DMA 1 mode register (DMAMR1)
2
R/W 32 bits 0x0000_0000 9.13.1.6.1/9-88
0x10584 DMA 1 status register (DMASR1)
2
R/W 32 bits 0x0000_0000 9.13.1.6.2/9-90
0x10588 DMA 1 current descriptor address register (DMACDAR1)
2
R/W 32 bits 0x0000_0000 9.13.1.6.3/9-91
0x10590 DMA 1 source address register (DMASAR1)
2
R/W 32 bits 0x0000_0000 9.13.1.6.4/9-92
0x10598 DMA 1 destination address register (DMADAR1)
2
R/W 32 bits 0x0000_0000 9.13.1.6.5/9-92
0x105A0 DMA 1 byte count register (DMABCR1) 2 R/W 32 bits 0x0000_0000 9.13.1.6.6/9-93
0x105A4 DMA 1 next descriptor address register (DMANDAR1) 2 R/W 32 bits 0x0000_0000 9.13.1.6.7/9-94
0x10600 DMA 2 mode register (DMAMR2) 2 R/W 32 bits 0x0000_0000 9.13.1.6.1/9-88
0x10604 DMA 2 status register (DMASR2) 2 R/W 32 bits 0x0000_0000 9.13.1.6.2/9-90
Table 3-1. Internal Memory Map (continued)
Address
(offset)
Register R/W Size Reset Section/Page