Freescale Semiconductor MPC8260 - Manual (Page 35)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xxxiii
Contents
Paragraph
Number
Title
Page
Number
30.10.2.3.5 AAL2 Protocol-Specific TCT ......................................................................... 30-57
30.10.2.3.6 VBR Protocol-Specific TCTE ......................................................................... 30-57
30.10.2.3.7 UBR+ Protocol-Specific TCTE....................................................................... 30-58
30.10.2.3.8 ABR Protocol-Specific TCTE ......................................................................... 30-59
30.10.3 OAM Performance Monitoring Tables .................................................................... 30-62
30.10.4 APC Data Structure ................................................................................................. 30-63
30.10.4.1 APC Parameter Tables ......................................................................................... 30-64
30.10.4.2 APC Priority Table .............................................................................................. 30-65
30.10.4.3 APC Scheduling Tables ....................................................................................... 30-65
30.10.5 ATM Controller Buffer Descriptors (BDs) .............................................................. 30-66
30.10.5.1 Transmit Buffer Operation................................................................................... 30-66
30.10.5.2 Receive Buffer Operation .................................................................................... 30-67
30.10.5.2.1 Static Buffer Allocation ................................................................................... 30-67
30.10.5.2.2 Global Buffer Allocation ................................................................................. 30-68
30.10.5.2.3 Free Buffer Pools ............................................................................................. 30-69
30.10.5.2.4 Free Buffer Pool Parameter Tables.................................................................. 30-70
30.10.5.3 ATM Controller Buffers....................................................................................... 30-71
30.10.5.4 AAL5 RxBD........................................................................................................ 30-71
30.10.5.5 AAL1 RxBD........................................................................................................ 30-73
30.10.5.6 AAL0 RxBD........................................................................................................ 30-74
30.10.5.7 AAL1 CES RxBD................................................................................................ 30-75
30.10.5.8 AAL2 RxBD........................................................................................................ 30-75
30.10.5.9 AAL5, AAL1 CES User-Defined Cell—RxBD Extension ................................. 30-76
30.10.5.10 AAL5 TxBDs....................................................................................................... 30-76
30.10.5.11 AAL1 TxBDs....................................................................................................... 30-77
30.10.5.12 AAL0 TxBDs....................................................................................................... 30-78
30.10.5.13 AAL1 CES TxBDs .............................................................................................. 30-79
30.10.5.14 AAL2 TxBDs....................................................................................................... 30-80
30.10.5.15 AAL5, AAL1 User-Defined Cell—TxBD Extension.......................................... 30-80
30.10.6 AAL1 Sequence Number (SN) Protection Table..................................................... 30-80
30.10.7 UNI Statistics Table ................................................................................................. 30-81
30.11 ATM Exceptions .......................................................................................................... 30-81
30.11.1 Interrupt Queues ...................................................................................................... 30-81
30.11.2 Interrupt Queue Entry .............................................................................................. 30-82
30.11.3 Interrupt Queue Parameter Tables ........................................................................... 30-83
30.12 The UTOPIA Interface ................................................................................................ 30-84
30.12.1 UTOPIA Interface Master Mode ............................................................................. 30-84
30.12.1.1 UTOPIA Master Multiple PHY Operation.......................................................... 30-85
30.12.2 UTOPIA Interface Slave Mode ............................................................................... 30-86
30.12.2.1 UTOPIA Slave Multiple PHY Operation ............................................................ 30-87
30.12.2.2 UTOPIA Clocking Modes ................................................................................... 30-87