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Freescale Semiconductor MPC8260 User Manual

Page 1352

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MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

Index-24

Freescale Semiconductor

S–S

Index

TxBD, 27-27

UART mode

character mode, 27-11
commands, 27-12
data handling, 27-11
error handling, 27-13
features list, 27-11
features not supported by SMCs, 27-10
frame format, 27-10
message-oriented mode, 27-11
overview, 27-10
parameter RAM, 27-6
programming example, 27-19
reception process, 27-11
RxBD, 27-13
transmission process, 27-11
TxBD, 27-17

Serial mode

parameter RAM configuration, 33-26

Serial peripheral interface (SPI)

block diagram, 38-1
clocking and pin functions, 38-2
commands, 38-12
configuring the SPI, 38-3
features list, 38-1
interrupt handling, 38-18
master mode, 38-3
maximum receive buffer length (MRBLR), 38-11
multi-master operation, 38-4
parameter RAM, 38-10
programming example

master, 38-16
slave, 38-17

programming model, 38-6
RxBD, 38-14
slave mode, 38-4
SPCOM, 38-10
SPIE, 38-9
SPIM, 38-9
SPMODE, 38-6
TxBD, 38-15

SI memory map, 3-22
SI memory map,, 3-13, 3-14, 3-15
SI RAM programming example, 15-14
SI,, 1-lxxx
SICR (SIU interrupt configuration register), 4-17
SICR,, 16-7
SIEXR (SIU external interrupt control register), 4-25
Signals

60x bus

TBST, 8-12
TCn, 8-12

TSIZn, 8-12
TTn, 8-9

byte-select signals, 11-75
chip-select signals, 11-74
clock signals, 10-5
general-purpose signals, 11-76
IDMA emulation

DACKx, 19-13
DONEx, 19-15
DREQx, 19-13

memory controller

byte-select signals, 11-10
EAMUX, 11-42
PSDVAL, 11-11, 11-58
SDRAM interface signals, 11-33
UPM interface signals, 11-63
UPM signal negation, 11-78
UPWAIT, 11-78

overview, 6-2

signals, external

description

EXTCLK,, 6-15

SIPMR_H (SIU high interrupt mask register), 4-22
SIPMR_L (SIU low interrupt mask register), 4-23
SIPNR_H (SIU high interrupt pending register), 4-21
SIPNR_L (SIU low interrupt pending register), 4-21
SIPRR (SIU interrupt priority register), 4-18
SIU memory map,, 3-1
SIUMCR (SIU module configuration register), 4-33
SIVEC (SIU interrupt vector register), 4-24
SMC memory map, 3-21
SMC,, 16-1
SMCE (SMC event) register

GCI mode, 27-34
transparent mode, 27-28
UART mode, 27-18

SMCM (SMC mask) register

GCI mode, 27-34
transparent mode, 27-28
UART mode, 27-18

SMCMRs (SMC mode registers), 27-2
SPCOM (SPI command) register, 38-10
SPI memory map, 3-21
SPIE (SPI event) register, 38-9
SPIM (SPI mask) register, 38-9
SPMODE (SPI mode) register, 38-6
SWR (software watchdog register), 4-7
SWSR (software service register), 4-38
SYPCR (system protection control register), 4-37
System integration timers memory map, 3-4
System interface unit (SIU)

60x bus monitor function, 4-2