Freescale Semiconductor MPC8260 - Manual (Page 398)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-92 Freescale Semiconductor
9.13.1.6.4 DMA Source Address Register [0–3] (DMASAR x )
The source address register, shown in Figure 9-85 , indicates the address where the DMA controller will be
reading data from. This address can be in either PCI memory or 60x memory. The software has to ensure
that this is a valid memory address.
The choice between PCI or 60x is done according to the following rule: If the address hits one of the PCI
outbound windows, then the source data is read from the PCI memory. Otherwise, it is read from the 60x
memory. Refer to
Figure 9-13 .
Figure 9-85. DMA Source Address Register [0–3] (DMASAR x)
Table 9-69 describes DMASARx fields.
9.13.1.6.5 DMA Destination Address Register [0–3] (DMADAR x )
The destination address register, shown in Figure 9-86 , indicates the address where the DMA controller
will be writing data to. This address can be in either PCI memory or 60x memory. The software has to
ensure that this is a valid memory address.
Table 9-68. DMACDAR x Field Descriptions
Bits Name Description
31–5 CDA Current descriptor address. Contains the current descriptor address of the segment
descriptor in memory. It must be aligned on an 8-word boundary.
4 SNEN Snoop enable. When set will allow snooping on DMA transactions.
3 EOSIE End-of-segment interrupt enable. When set will generate an interrupt if the current DMA
transfer for the current descriptor is finished.
2–0 — Reserved, should be cleared.
31 16
Field SA
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10512(DMASAR0); 0x10592 (DMASAR1); 0x10612 (DMASAR2); 0x10692 (DMASAR3)
15 0
Field SA
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10510 (DMASAR0); 0x10590 (DMASAR1); 0x10610 (DMASAR2); 0x10690 (DMASAR3)
Table 9-69. DMASAR x Field Descriptions
Bit Name Description
31–0 SA Source address of DMA transfer. The content is updated after every DMA read operation.