Freescale Semiconductor MPC8260 - Manual (Page 444)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-26 Freescale Semiconductor
11.3.5 Machine A/B/C Mode Registers (M x MR)
The machine x mode registers (MxMR), shown in Figure 11-11 , contain the configuration for the three
UPMs.
Table 11-10 describes MxMR bits.
28 EAMUX External address multiplexing enable/disable.
0 No external address multiplexing. Fastest timing.
1 The memory controller asserts SDAMUX for an extra cycle before issuing an
ACTIVATE
command to the SDRAM. This is useful when external address multiplexing can cause a
delay on the address lines. Note that if EAMUX is set, ACTTORW should be at least 2.
In local bus mode, external address multiplexing is placed on the address lines. If the additional
delay of the multiplexing endangers the device setup time, EAMUX should be set. Setting this
bit causes the memory controller to add another cycle for each address phase.
Note: EAMUX can also be set in case of address line delays, such as address buffers. See
Section 11.4.6.7, “External Address Multiplexing Signal .”
29 BUFCMD If external buffers are placed on the control lines going to both the SDRAM and address lines,
setting BUFCMD causes all SDRAM control lines except CS to be asserted for two cycles,
instead of one. See
Section 11.4.6.8, “External Address and Command Buffers (BUFCMD) .”
0 Normal timing for the control lines
1 All control lines except CS are asserted for two cycles
In 60x-compatible mode, external buffers may be placed on the command strobes, except CS,
as well as the address lines. If the additional delay of the buffers is endangering the device
setup time, BUFCMD should be set to cause the memory controller to add another cycle for
each SDRAM command.
30–31 CL CAS latency. Defines the timing for first read data after a column address is sampled by the
SDRAM. See
Section 11.4.6.3, “Column Address to First Data Out—CAS Latency .”
00 Reserved
01 1 clock cycle
10 2 clock cycles
11 3 clock cycles
0 1 2 3 4 5 7 8 9 10 12 13 14 15
Field BSEL RFEN OP — AM x DSx G0CLx GPL_x4DIS RLFx
Reset 0000_0000_0000_0 1 00
R/W R/W
Addr 0x0x10170 (MAMR); 0x0x10174 (MBMR); 0x0x10178 (MCMR)
16 17 18 21 22 25 26 31
Field RLFx WLF x TLF x MAD
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10172 (MAMR); 0x10176 (MBMR); 0x1017A (MCMR)
Figure 11-11. Machine x Mode Registers (MxMR)
Table 11-9. LSDMR Field Descriptions (continued)
Bits Name Description